CY62148ESL MoBL
®
Document #: 001-50045 Rev. **
Page 7 of 10
Switching Waveforms
Figure 3. Read Cycle No. 1
(Address Transition Controlled)
[13, 14]
Figure 4. Read Cycle No. 2
(OE Controlled)
[14, 15]
Figure 5. Write Cycle No. 1
(WE Controlled, OE HIGH During Write)
[16, 17]
PREVIOUS DATA VALID
DATA VALID
RC
t
AA
t
OHA
t
RC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
IMPEDANCE
I
CC
I
SB
HIGH
ADDRESS
CE
DATA OUT
V
CC
SUPPLY
CURRENT
OE
DATA VALID
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
ADDRESS
CE
WE
DATA IO
OE
NOTE 18
Notes
13. Device is continuously selected. OE, CE = V
IL
.
14. WE is HIGH for read cycles.
15. Address valid before or similar to CE transition LOW.
16. Data IO is high impedance if OE = V
IH
.
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
18. During this period, the IOs are in output state. Do not apply input signals.
[+] Feedback
