CY14B101K
Document Number: 001-06401 Rev. *I
Page 8 of 28
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystal oscillators typically
have an error of +20ppm to +35ppm. However, CY14B101K
employs a calibration circuit that improves the accuracy to +1/–2
ppm at 25°C. This implies an error of +2.5 seconds to -5 seconds
per month.
The
calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in Calibration register at 0x1FFF8. The
calibration bits occupy the five lower order bits in the Calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it corre-
sponds to an adjustment of 4.068 or –2.034 ppm offset in oscil-
lator error, depending on the sign.
Calibration occurs within a 64 minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the 64
minute cycle is modified. If a binary 6 is loaded, the first 12 are
affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the Calibration register.
To determine the required calibration, the CAL bit in the Flags
register (0x1FFF0) must be set to ‘1’. This causes the INT pin to
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
Note
Setting or changing the Calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit “W” (in the flags register at
0x1FFF0) to “1” to enable writes to the Flag register. Write a
value to CAL, and then reset the write bit to “0” to disable writes.
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x1FFF1-5) with the corre-
sponding time of day and date values. When a match occurs, the
alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set.
There are four alarm match fields - date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x1FFF0 indicates that a date or time match has occurred. The
AF bit is set to “1” when a match occurs. Reading the flags or
control register clears the alarm flag bit (and all others). A
hardware interrupt pin may also be used to detect an alarm
event.
Note
CY14B101K requires the alarm match bit for seconds
(0x1FFF2 - D7) to be set to ‘0’ for proper operation of Alarm Flag
and Interrupt.
Alarm registers are not nonvolatile and, therefore, need to be
reinitialized by software on power up. To set, clear or enable an
alarm, set the ‘W’ bit (in Flags Register - 0x1FFF0) to ‘1’ to
enable writes to Alarm Registers. After writing the alarm value,
clear the ‘W’ bit back to “0” for the changes to take effect.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator must be running for the watchdog to function. It
begins counting down from the value loaded in the Watchdog
Timer register.
The timer consists of a loadable register and a free running
counter. On power up, the watchdog time out value in register
0x1FFF7 is loaded into the Counter Load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of ‘0’. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
You can prevent the time out interrupt by setting WDS bit to ‘1’
prior to the counter reaching ‘0’. This causes the counter to
reload with the watchdog time out value and to be restarted. As
long as the user sets the WDS bit prior to the counter reaching
the terminal value, the interrupt and WDT flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in
Figure 4
. Note that setting the
watchdog time out value to ‘0’ disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. The flag is set upon a
watchdog time out and cleared when the user reads the Flags or
Control registers. If the watchdog time out occurs, the user also
enables an optional interrupt source to drive the INT pin.
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