CyberResearch CPBF PMX-233, Руководство пользователя

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17
• JP8(5-10): WDT Time - Out Period
PERIOD 5-6 7-8 9-10
*1 sec ON ON ON
2 sec OFF ON ON
10 sec ON OFF ON
20 sec OFF OFF ON
110 sec ON ON OFF
220 sec OFF ON OFF
The Watchdog timer is disabled after the system Power On. The
watchdog timer can be enabled by an Enable cycle by reading the
control port (443H), a Refresh cycle by reading the control port (443H)
and a Disable cycle by reading the Watchdog timer disable control port
(045H). After a Enable cycle of WDT,
the user must constantly proceed a
Refresh cycle to WDT before its period setting comes at the end of every
1, 2, 10, 20, 110 or 220 seconds
(Please reference to the selection table of JP8 for WDT Time-Out period
setting). If the Refresh cycle does not
activate before the WDT
period cycle, the on - board WDT architecture will issue a Reset or
NMI cycle to the system.
The Watch d og Timer is controlled by two I/O ports.
443H I/O Read The Enable cycle.
443H I/O Read The Refresh cycle.
045H I/O Read The Disable cycle.