Curtiss-Wright FHK4-FM4MWB04-00, Справочник по аппаратуре, Страница: 108 / 123

REHOSTABLE CMC FPDP INTERFACE
Copyright 2012 11-8 FibreXtreme HW Reference for FPDP Cards
11.4.2 Source Card Signal Interconnects
A source card for the system has to have the P3 interface and the P6 interface wired for
operation. The P6 connector is the FPDP receiver interface.
Table 11-4 lists the signal connections for the P6 connector. An asterisk “*” is used to
designate signals that are common on the P4 and P6 connectors. All RESERVED pins
should be tied to a 10 k
Ω
resistor tied to ground. Table 11-5 gives descriptions of these
signals. Figure 11-3 provides a visual description of notes 1 and 2.
WARNING : PIO1_IN and PIO2_IN are shared between the transmit and receive
FPDP connectors on the rehostable CMC FPDP card. Do not drive PIO1_IN and
PIO2_IN on the transmit and receive connectors with different voltage levels. Doing so
may damage the circuit or the CMC FPDP card.
NOTE 1 : /RDIR, PIO1_IN, PIO2_IN, and /TNRDY are encoded into the Serial FPDP
data stream by the encoder logic at the appropriate time during the framing sequence.
To guarantee a pulse on these signals is propagated to the remote Serial FPDP receiver,
the pulse width must be equal to or greater than the maximum time between the
respective ordered sets, which is 521 reference clock periods (up to 512 words of data
in each frame with an overhead of up to nine ordered sets). The reference clock is
typically driven by an on-board oscillator. The standard reference clock frequency for
SL100 is 53.125 MHz, while the standard reference clock frequency for SL240 is 125
MHz. These signals do not propagate through the Transmit FIFO within the
SL100/SL240 CMC card and thus cannot be directly associated with the corresponding
data. Their use is not affected by the state of the Disable Transmitter bit in the Link
Control register. Thus, /RDIR, PIO1_IN, PIO2_IN, and /TNRDY are transmitted onto
the link regardless of if the transmission of link data is enabled.
In non-loop operation (LWRAP = ‘0’ in the Link Control register), /RDIR, PIO1_IN,
PIO2_IN, and /TNRDY are directly inserted into the Serial FPDP data stream based on
the values of the signals from the FPDP interface. If Loop (or Copy) mode is selected
(LWRAP = ‘1’), the values of PIO1_IN and PIO2_IN are retransmitted according to
their received link values and the values of /RDIR and /TNRDY are used as follows: if
the receive interface is enabled (Disable Receiver = ‘0’ in the Link Control register),
the values transmitted are the received link values logically ORed with the FPDP-
interface values; otherwise, the values are retransmitted according to their received link
values. The use of /RDIR and /TNRDY is consistent with the use of flow control
(retransmission of a STOP request) for loop operations. See the ANSI/VITA 17.1
Serial FPDP specification for additional details.
NOTE 2 : /TDIR, PIO1_OUT, PI02_OUT, and /RNRDY are decoded from the Serial
FPDP data stream by the decoder logic and are latched based on the last value received
by the data stream. These signals do not propagate through the Receive FIFO within the
SL100/SL240 CMC card and thus cannot be directly associated with the corresponding
data. Their use is not affected by the state of the Disable Receiver bit in the Link
Control register. Thus, /TDIR, PIO1_OUT, PIO2_OUT, and /RNRDY are received
from the link regardless of if the reception of link data is enabled.