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REHOSTABLE CMC FPDP INTERFACE
Copyright 2012 11-11 FibreXtreme HW Reference for FPDP Cards
Table 11-5 Signal Descriptions for FPDP Receiver Interface (P6)
Signal Name Signal
Direction
Signal Description
RD[31:0] Input Receive Data Bus . This is data from the FPDP interface to the Transmit FIFO of the
SL240 card. It is placed in the Transmit FIFO on a rising edge of RSTROBE with
/RDVALID asserted.
/RDIR Input
Receive Data Direction . This is the data direction signal from the FPDP interface. It
has no affect on SL240 card operation. See note 1 for additional information on its
operation.
/RDVALID Input
Receive Data Valid . Set to ‘0’ to place the data on the RD[31:0] bus in the Transmit
FIFO of the SL240 card on this clock. Set to ‘1’ to not place the data on the RD[31:0]
bus in the Transmit FIFO.
RERROR Output
Receive Error . A ‘1’ indicates the link interface is down and flow control is not ignored
(IGNORE_FC = ‘0’); A ‘0’ indicates the error has not occurred. RERROR is asserted
for at least four RSTROBE periods.
/RNRDY Output Receive Not Ready . A ‘0’ indicates the FPDP receiver is not ready to accept data. A
‘1’ indicates the FPDP receiver is ready to accept data. /RDVALID or /RSYNC should
not be asserted while /RNRDY is asserted. See note 2 for additional information on its
operation.
PIO1_IN Input Programmable I/O 1 . This is a user-defined input that is passed straight to the
encoder interface and embedded in the data stream. This input line is shared with the
FPDP transmitter interface (P4). See note 1 for additional information on its operation.
PIO2_IN Input
Programmable I/O 2 . This is a user-defined input that is passed straight to the
encoder interface and embedded in the data stream. This input line is shared with the
FPDP transmitter interface (P4). See note 1 for additional information on its operation.
PIO1_OUT Output
Programmable I/O 1 . This is a user-defined output that is removed from the data
stream at the decoder interface. This output line is shared with the FPDP transmitter
interface (P4). See note 2 for additional information on its operation.
PIO2_OUT Output Programmable I/O 2 . This is a user-defined output that is removed from the data
stream at the decoder interface. This output line is shared with the FPDP transmitter
interface (P4). See note 2 for additional information on its operation.
/RESET Input Global Reset . Set to ‘0’ to perform a global reset of the SL240 card including state
machines, FIFOs, and output signals. Set to ‘1’ for normal operation. For a power-on
reset, /RESET must be asserted for at least 10 ms after the power has reached
3.13 V. Any time /RESET is asserted after a valid power level has been achieved, the
reset is asynchronous and /RESET must be asserted for at least 150 ns. This signal
is common with the FPDP transmitter interface (P4).
RSTROBE Input FPDP Receiver Clock . This is the clock input for the receiver interface. All receiver
signals are timed off the rising edge of this clock. RSTROBE should be a free-running
clock. RSTROBE has a maximum frequency of 26.5625 MHz for SL100 and 62.5
MHz for SL240. RSTROBE is terminated on the CMC card as shown in Figure G-4.
/RSUSPEND Output Receive Suspend . This signal asserts flow control from the SL240 card. A ‘0’
indicates the SL240 card’s Transmit FIFO has room for not more than 16 data words.
A ‘1’ indicates there is room for more than 16 data words in the Transmit FIFO.
/RSYNC Input
Receive Synchronization . Set to ‘0’ to assert /RSYNC. This signal is used for
framing data or synchronizing source and destination nodes. It will remain
synchronized with the data stream. The default value of /RSYNC is ‘0.’ Do not leave
this signal float or tie it to ‘0.’ If it is continually ‘0,’ link throughput is dramatically
decreased since every Serial FPDP frame will be a SYNC with DATA frame, which
contains only one data word.