Curtiss-Wright FHK4-FM4MWB04-00, Справочник по аппаратуре

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REHOSTABLE CMC FPDP INTERFACE
Copyright 2012 11-10 FibreXtreme HW Reference for FPDP Cards
Table 11-4 FPDP Receiver Interface (P6)
Pin
Input
Lines
Output
Lines Pin
Input
Lines
Output
Lines
A1 PIO2_IN* B2 PIO2_OUT*
A3 +5 V B4 PIO1_IN*
A5 RERROR B6 PIO1_OUT*
A7 /RNRDY B8 GND
A9 GND B10 /RSUSPEND
A11 RSTROBE B12 GND
A13 GND B14 /RDVALID
A15 /RESET* B16 GND
A17 RESERVED B18 /RDIR
A19 /RSYNC B20 RESERVED
A21 RD31 B22 +5 V
A23 GND B24 RD30
A25 RD29 B26 RD28
A27 RD27 B28 GND
A29 RD26 B30 RD25
A31 GND B32 RD24
A33 RD23 B34 RD22
A35 RD21 B36 GND
A37 RD20 B38 RD19
A39 +5 V B40 RD18
A41 RD17 B42 RD16
A43 RD15 B44 GND
A45 RD14 B46 RD13
A47 GND B48 RD12
A49 RD11 B50 RD10
A51 RD9 B52 +5 V
A53 RD8 B54 RD7
A55 GND B56 RD6
A57 RD5 B58 RD4
A59 RD3 B60 GND
A61 RD2 B62 RD1
A63 +5 V B64 RD0
* These signals are common on the P4 and P6 connectors.
Certain signals are important for the transmitter interface, while others are important only
for the receive interface. In the following signal descriptions, a ‘1’ refers to a logic high
level (above 2.0 V), while a ‘0’ refers to a logic low level (less than 0.8 V). All signals
use the LVTTL Input/Output standard.