Symbol
Parameter
Min
Typ
Max
Unit
f
sclk
PCM clock frequency (Slave mode: input)
64
-
(a)
kHz
f
sclk
PCM clock frequency (GCI mode)
128
-
(b)
kHz
t
sclkl
PCM_CLK low time
200
-
-
ns
t
sclkh
PCM_CLK high time
200
-
-
ns
t
hsclksynch
Hold time from PCM_CLK low to PCM_SYNC high
2
-
-
ns
t
susclksynch
Set-up time for PCM_SYNC high to PCM_CLK low
20
-
-
ns
t
dpout
Delay time from PCM_SYNC or PCM_CLK,
whichever is later, to valid PCM_OUT data (Long
Frame Sync only)
-
-
20
ns
t
dsclkhpout
Delay time from CLK high to PCM_OUT valid data
-
-
15
ns
t
dpoutz
Delay time from PCM_SYNC or PCM_CLK low,
whichever is later, to PCM_OUT data line high
impedance
-
-
15
ns
t
supinsclkl
Set-up time for PCM_IN valid to CLK low
20
-
-
ns
t
hpinsclkl
Hold time for PCM_CLK low to PCM_IN invalid
2
-
-
ns
Table 9.7: PCM Slave Timing
(a)
Max frequency is the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK
(b)
Max frequency is twice the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK
Advance Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2011
Page 54 of 110
CS-209182-DSP1
CSR8640 BGA
Data Sheet
