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9.1

Audio Input and Output

The audio input circuitry consists of:

■

2 independent 16-bit high-quality ADC channels:

■

Programmable as either microphone or line input

■

Programmable as either stereo or dual-mono inputs

■

Multiplexed with 1 of the digital microphone inputs, see Figure 9.2 and Section 9.2.14

■

Each channel is independently configurable to be either single-ended or fully differential

■

Each channel has an analogue and digital programmable gain stage for optimisation of different

microphones

■

2 digital microphone inputs (MEMS)

The audio output circuitry consists of a dual differential class A-B output stage.

9.2

Audio Codec Interface

The main features of the interface are:

■

Stereo and mono analogue input for voice band and audio band

■

Stereo and mono analogue output for voice band and audio band

■

Support for I²S stereo digital audio bus standard

■

Support for PCM interface including PCM master codecs that require an external system clock

Important Note:

To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right

channel for audio output. With respect to audio input, software and any registers, channel 0 or channel A

represents the left channel and channel 1 or channel B represents the right channel.

Advance Information

This material is subject to CSR's non-disclosure agreement

Page 37 of 110

CS-209182-DSP1

www.csr.com

CSR8640 BGA

Data Sheet

Содержание BlueCore CSR8640 BGA

Страница 1: ...olution for DSP Intensive Audio Applications 2 mic CVC Audio Enhancement Fully Qualified Single chip Bluetooth v3 0 System Advance Information CSR8640A03 Issue 1 2 4GHz Radio Balun I O BT_RF RAM Baseb...

Страница 2: ...SPI flash memory interface SPI interface for debug and programming I C interface for EEPROM Up to 22 general purpose PIOs PCM and I S interfaces 3 LED drivers includes RGB with PWM flasher independent...

Страница 3: ...handsets for voice Multipoint support for A2DP connection to 2 A2DP sources for music playback Talk time extension Headset Configurator Tool Configures the CSR8640 stereo headset ROM software feature...

Страница 4: ..._1V35 SMPS_1V8_SENSE 3V3_USB Voltage Temperature Monitor BT_RF Clock Generation AUX ADC XTAL AIO 0 MIC_AP MIC_BN MIC_BP SPKR_LP SPKR_RN SPKR_RP SENSE SENSE Bluetooth Baseband Bluetooth Radio and Balun...

Страница 5: ...you have any comments about this document email comments csr com giving number title and section with your feedback Advance Information This material is subject to CSR s non disclosure agreement Camb...

Страница 6: ...ill not warrant the use of its devices in such applications CSR Green Semiconductor Products and RoHS Compliance CSR8640 BGA devices meet the requirements of Directive 2002 95 EC of the European Parli...

Страница 7: ...cal Layer Hardware Engine 24 3 Clock Generation 25 3 1 Clock Architecture 25 3 2 Input Frequencies and PS Key Settings 25 3 3 Crystal Oscillator XTAL_IN and XTAL_OUT 25 3 3 1 Crystal Calibration 25 3...

Страница 8: ...Filter 46 9 3 PCM1 Interface 47 9 3 1 PCM Interface Master Slave 48 9 3 2 Long Frame Sync 49 9 3 3 Short Frame Sync 49 9 3 4 Multi slot Operation 49 9 3 5 GCI Interface 50 9 3 6 Slots and Sample Form...

Страница 9: ...r Enable 79 13 3 4 Battery Charger 79 13 3 5 USB 81 13 3 6 Clocks 81 13 3 7 Stereo Codec Analogue to Digital Converter 82 13 3 8 Stereo Codec Digital to Analogue Converter 83 13 3 9 Digital 84 13 3 10...

Страница 10: ...ation 103 18 1 Tape Orientation 103 18 2 Tape Dimensions 103 18 3 Reel Information 104 18 4 Moisture Sensitivity Level 104 19 Document References 105 Terms and Definitions 106 List of Figures Figure 1...

Страница 11: ...ration 65 Figure 11 1 Battery Charger Mode to Mode Transition Diagram 70 Figure 11 2 Battery Charger External Mode Typical Configuration 72 Figure 16 1 Programmable Audio Prompts in External SPI Flash...

Страница 12: ...ation Using PSKEY_ANA_FTRIM_OFFSET 26 Equation 3 2 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2402 0168MHz 26 Equation 3 3 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2401 9832MHz 26 Equation 7 1 Bau...

Страница 13: ...C1 D1 E1 F1 G1 H1 J1 B1 K2 A2 C2 D2 E2 F2 G2 H2 J2 B2 K3 A3 J3 B3 K4 A4 J4 B4 K5 A5 J5 B5 K8 A8 J8 B8 K9 A9 C9 D9 E9 F9 G9 H9 J9 B9 K6 A6 J6 B6 K7 A7 J7 B7 F5 E5 F6 E6 Figure 1 1 Device Pinout Advanc...

Страница 14: ...PIO 1 PIO 13 PIO 11 PIO 9 PIO 7 PIO 2 PIO 17 SMPS_1V8_SENSE USB_P PIO 5 LED 0 RST SPI_PCM PIO 3 CHG_EXT VBAT_SENSE VSS_SMPS_1V8 3V3_USB USB_N LED 1 VDD_DIG_MEM VREGIN_DIG VREGENABLE VCHG LX_1V8 VBAT L...

Страница 15: ...PI and PCM1 interfaces are mapped as alternative functions on the PIO port PIO Port Ball Pad Type Supply Domain Description PIO 21 D10 Bidirectional with weak pull down VDD_PADS_2 Programmable input o...

Страница 16: ...flash chip select I2C_WP I C bus memory write protect line PIO 11 G2 Bidirectional with strong pull down VDD_PADS_1 Programmable input output line 11 Alternative function QSPI_IO 0 serial quad I O fl...

Страница 17: ...put PCM1_IN PCM1 synchronous data input PIO 1 F10 Bidirectional with strong pull up VDD_PADS_2 Programmable input output line 1 PIO 0 F9 Bidirectional with strong pull up VDD_PADS_2 Programmable input...

Страница 18: ...lternative function programmable output PIO 31 Note As output is open drain an external pull up is required when PIO 31 is configured as a programmable output LED 1 K1 LED driver Alternative function...

Страница 19: ...1 35V supply see Section 12 for connections VDD_AUDIO A7 Positive supply for audio Connect to 1 35V supply see Section 12 for connections VDD_AUDIO_DRV B5 Positive supply for audio output amplifiers...

Страница 20: ...or analogue circuitry and Bluetooth radio local oscillator VSS_BT_RF B3 Bluetooth radio ground VSS_DIG F6 Ground connection for internal digital circuitry VSS_SMPS_1V35 K9 1 35V switch mode regulator...

Страница 21: ...5 5 5 5 55 Ball diam 0 3 E1 4 5 Solder land opening 0 275 Notes 1 Dimension b is measured at the maximum solder ball diameter parallel to datum plane C 2 Datum C seating plane is defined by the spheri...

Страница 22: ...needs to take into consideration its current carrying and the RF requirements 35 m thick 1oz copper lands are recommended rather than 17 m thick 0 5oz This results in a greater standoff which has bee...

Страница 23: ...that no discriminator tank is needed and its excellent performance in the presence of noise enables CSR8640 BGA to exceed the Bluetooth requirements for co channel and adjacent channel rejection For...

Страница 24: ...smission the BMC constructs a packet from header information previously loaded into memory mapped registers by the software and payload data voice taken from the appropriate ring buffer in the RAM Dur...

Страница 25: ...al crystals 3 3 1 Crystal Calibration The actual crystal frequency depends on the capacitance of XTAL_IN and XTAL_OUT on the PCB and the CSR8640 BGA as well as the capacitance of the crystal Correct c...

Страница 26: ...RIM_OFFSET value is 7 0xfff9 see Equation 3 3 PSKEY_ANA_FTRIM_OFFSET 2401 9832 2402 1 220 7 Equation 3 3 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2401 9832MHz 3 3 2 Crystal Specification Table 3 1...

Страница 27: ...interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and host interfaces 4 1 VM Accelerator CSR8640 BGA contains a VM accelerator alongside the MCU Thi...

Страница 28: ...DM2 DSP Data Memory 1 Interface DM1 DSP Program Memory Interface PM Figure 5 1 Kalimba DSP Interface to Internal Functions The key features of the DSP include 80MIPS performance 24 bit fixed point DSP...

Страница 29: ...x 32 bit for program memory PM 6 4 Internal ROM Internal ROM is provided for system firmware implementation 6 5 Serial Flash Interface CSR8640 BGA supports external serial flash ICs This enables addit...

Страница 30: ...ines as well as PCB tracks and the effects of ferrite beads USB suspend modes and Bluetooth low power modes Global suspend Selective suspend includes remote wake Wake on Bluetooth includes permitted d...

Страница 31: ...Parity None Odd or Even Number of stop bits 1 or 2 Bits per byte 8 Table 7 1 Possible UART Settings Note Load the DFU boot loader into the internal ROM before using the UART or USB interface Use the S...

Страница 32: ...ternally CSR provides development and production tools to communicate over the SPI from a PC although a level translator circuit is often required All are available from CSR 7 3 1 Multi slave Operatio...

Страница 33: ...C_WP 2 2k R3 2 2k R2 2 2k R1 Figure 7 2 Example I C EEPROM Connection Note The I C EEPROM requires external pull up resistors see Figure 7 2 CSR recommends 400kHz capable I C EEPROMs Advance Informati...

Страница 34: ...nt software release note for the implementation of these PIO lines as they are firmware build specific 8 2 Analogue I O Ports AIO CSR8640 BGA has 1 general purpose analogue interface pin AIO 0 Typical...

Страница 35: ...lculated ILED VDD V F R LED R ON Equation 8 1 LED Current For the LED pads to act as resistance the external series resistor RLED needs to be such that the voltage drop across it VR keeps VPAD below 0...

Страница 36: ...Port Register Interface Voice Port Registers PCM1 Digital Audio Stereo Audio Codec Driver PCM1 Interface 2 x Differential DAC Outputs 2 x Differential ADC Inputs Digital MICs 2 x Digital MICs Figure 9...

Страница 37: ...o Codec Interface The main features of the interface are Stereo and mono analogue input for voice band and audio band Stereo and mono analogue output for voice band and audio band Support for I S ster...

Страница 38: ...which results in low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude It operates from a dual power supply VDD_AUDIO for the audio circuits and VDD_AU...

Страница 39: ...ADC pre amplifier and ADC analogue amplifier The ADC pre amplifier has 4 gain settings 0dB 9dB 21dB and 30dB The ADC analogue amplifier gain is 3dB to 12dB in 3dB steps The overall analogue gain for t...

Страница 40: ...of 2 fourth order Sigma Delta converters enabling 2 separate channels that are identical in functionality as Figure 9 2 shows 2 gain stages for each channel 1 of which is an analogue gain stage and t...

Страница 41: ...ll gain control of the DAC Its setting is a combined function of the digital and analogue amplifier settings Analogue Gain Selection Value DAC Analogue Gain Setting dB Analogue Gain Selection Value DA...

Страница 42: ...The input impedance at MIC_AN MIC_AP MIC_BN and MIC_BP is typically 6k C1 C2 C3 and C4 are 100 150nF if bass roll off is required to limit wind noise on the microphone R1 and R2 set the microphone loa...

Страница 43: ...e left and right selection for the digital microphones are appropriately pulled up or down for selection on the PCB 9 2 15 Line Input Section 9 2 4 states that if the pre amplifier audio input gain is...

Страница 44: ...R_LN and SPKR_LP for the left channel and between SPKR_RN and SPKR_RP for the right channel G TW 0005537 1 1 SPKR_LP SPKR_LN SPKR_RP SPKR_RN Figure 9 7 Speaker Output 9 2 17 Mono Operation Mono operat...

Страница 45: ...DAC interface see Figure 9 8 G TW 0005375 1 1 Side Tone Route Digital Input Analogue Output Digital Output Analogue Input Digital Gain Demux Mux DAC DAC Interface Side Tone Digital Gain ADC ADC Inter...

Страница 46: ...0 BGA has a programmable digital filter integrated into the ADC channel of the codec The filter is a 2 stage second order IIR and is for functions such as custom wind noise reduction The filter also h...

Страница 47: ...n 1 b01 z 1 b02 z 2 1 a 01 z 1 a 02 z 2 1 b11 z 1 b12 z 2 1 a 11 z 1 a 12 z 2 Equation 9 1 IIR Filter Transfer Function H z Filter with DC Blocking HDC z H z 1 z 1 Equation 9 2 IIR Filter Plus DC Bloc...

Страница 48: ...K Various clock formats including Long Frame Sync Short Frame Sync GCI timing environments 13 bit or 16 bit linear 8 bit law or A law companded sample formats Receives and transmits on any selection o...

Страница 49: ...osition or on the rising edge 9 3 3 Short Frame Sync In Short Frame Sync the falling edge of PCM_SYNC indicates the start of the PCM word PCM_SYNC is always 1 clock cycle long G TW 0000220 2 3 PCM_SYN...

Страница 50: ...ated by the rising edge of PCM_SYNC and runs at 8kHz 9 3 6 Slots and Sample Formats CSR8640 BGA receives and transmits on any selection of the first 4 slots following each sync pulse Slot durations ar...

Страница 51: ...ample and zeros padding selected A 16 bit slot with 13 bit linear sample and sign extension selected A 16 bit slot with 13 bit linear sample and audio gain selected Figure 9 15 16 bit Slot Length and...

Страница 52: ...to valid PCM_OUT 20 ns tdmclklsyncl Delay time from PCM_CLK low to PCM_SYNC low Long Frame Sync only 20 ns tdmclkhsyncl Delay time from PCM_CLK high to PCM_SYNC low 20 ns tdmclklpoutz Delay time from...

Страница 53: ...Long Frame Sync G TW 0000225 3 3 PCM_SYNC PCM_CLK PCM_OUT PCM_IN MSB LSB LSB MSB MSB LSB LSB MSB fmlk tmclkh tmclkl t supinclkl t t dmclkpout thpinclkl dmclkhsyncl t dmclklpoutz t dmclkhpoutz tr t f...

Страница 54: ...hpout Delay time from CLK high to PCM_OUT valid data 15 ns tdpoutz Delay time from PCM_SYNC or PCM_CLK low whichever is later to PCM_OUT data line high impedance 15 ns tsupinsclkl Set up time for PCM_...

Страница 55: ...M_IN MSB LSB LSB MSB fsclk tsclkh ttsclkl t hsclksynch t susclksynch tdpoutz tdpoutz t supinsclkl t hpinsclkl tr t f LSB MSB MSB LSB t dsclkhpout Figure 9 19 PCM Slave Timing Short Frame Sync 9 3 9 PC...

Страница 56: ...MODE 9 3 10 PCM Configuration Configure the PCM by using PSKEY_PCM_CONFIG32 and PSKEY_PCM_USE_LOW_JITTER_MODE see your PS Key file The default for PSKEY_PCM_CONFIG32 is 0x00800000 i e first slot follo...

Страница 57: ...Modes The internal representation of audio samples within CSR8640 BGA is 16 bit and data on SD_OUT is limited to 16 bit per channel Symbol Parameter Min Typ Max Unit SCK Frequency 6 2 MHz WS Frequency...

Страница 58: ...me 20 ns tih SCK high to SD_IN invalid hold time 2 5 ns Table 9 10 I S Slave Mode Timing G TW 0000231 2 2 SD_OUT SD_IN t t t t t t WS Input SCK Input ch opd ih sh ssu cl isu t Figure 9 21 Digital Audi...

Страница 59: ...D_IN valid to SCK high set up time 18 44 ns tih SCK high to SD_IN invalid hold time 0 ns Table 9 12 I S Master Mode Timing Parameters WS and SCK as Outputs G TW 0000232 2 2 WS Output SCK Output SD_OUT...

Страница 60: ...ion configuration for the CSR8640 BGA A 1 80V single supply rail system using the 1 80V switch mode regulator A 1 80V parallel supply rail system for higher currents using the 1 80V and 1 35V switch m...

Страница 61: ...ooth SMPS_1V8_SENSE SMPS_1V35_SENSE SENSE IN OUT OUT VDD_AUX SENSE OUT OUT VDD_ANA_RADIO SENSE IN SENSE Auxiliary Circuits VDD_BT_LO IN IN Digital Core Circuits VDD_DIG Regulator OUT SENSE IN VDD_DIG_...

Страница 62: ...uetooth SMPS_1V8_SENSE SMPS_1V35_SENSE SENSE IN OUT OUT VDD_AUX SENSE OUT OUT VDD_ANA_RADIO SENSE IN SENSE Auxiliary Circuits VDD_BT_LO IN IN Digital Core Circuits VDD_DIG Regulator OUT SENSE IN VDD_D...

Страница 63: ...o meet the specifications in Section 13 3 1 1 requires a total resistance of 1 0 0 5 recommended for the following The track between the battery and VBAT The track between LX_1V8 and the inductor The...

Страница 64: ...owing enable the 1 35V switch mode regulator VREGENABLE pin The CSR8640 BGA firmware with reference to PSKEY_PSU_ENABLES VCHG pin The switching frequency is adjustable by setting an offset from 4 00MH...

Страница 65: ...and VBAT The track between LX_1V8 LX_1V35 and the inductor The inductor L1 ESR The track between the inductor L1 and the sense point on the 1 80V supply rail The following enable the 1 80V switch mode...

Страница 66: ...enables the CSR8640 BGA and the following regulators 1 8V switch mode regulator 1 35V switch mode regulator Low voltage VDD_DIG linear regulator Low voltage VDD_AUX linear regulator The VREGENABLE pi...

Страница 67: ...tal bidirectional N A PIO 0 Digital bidirectional PUS PIO 1 Digital bidirectional PUS PIO 2 Digital bidirectional PDW PIO 3 Digital bidirectional PDW PIO 4 Digital bidirectional PDW PIO 5 Digital bidi...

Страница 68: ...in States on Reset Note PUS Strong pull up PDS Strong pull down PUW Weak pull up PDW Weak pull down 10 10 2 Status After Reset The status of CSR8640 BGA after a reset is Warm reset baud rate and RAM d...

Страница 69: ...n provide up to 200mA of charge current for currents higher than this the CSR8640 BGA can control an external pass transistor see Section 11 5 Mode Battery Charger Enabled VBAT_SENSE Disabled No X Tri...

Страница 70: ...eases to Ifast Ifast is between 10mA and 200mA set by PS Key or a VM trap In addition Ifast is calibrated in production test to correct for process variation in the charger circuit The current is held...

Страница 71: ...ttings for the charger current depend on the battery capacity and type which are set by the user in the PS Keys For more information on the CSR8640 BGA including details on setting up calibrating trim...

Страница 72: ...nal Pass Device R1 220m C1 4 7 F Figure 11 2 Battery Charger External Mode Typical Configuration Advance Information This material is subject to CSR s non disclosure agreement Cambridge Silicon Radio...

Страница 73: ...th through GND plane for SMPSU current from C4 to VSS_SMPS_1V8 and C7 to VSS_SMPS_1V35 Ensure routing from L2 to ball K3 and from L2 to C8 C9 and ball C2 are kept separate CSR recommends low Rdc induc...

Страница 74: ...V 1 8V VDD_AUDIO_DRV 0 4 1 95 V VDD_AUX_1V8 0 4 1 95 V VDD_PADS_1 0 4 3 60 V VDD_PADS_2 0 4 3 60 V VDD_AUX_1V8 0 4 1 95 V 1 35V SMPS_1V35_SENSE 0 4 1 45 V VDD_AUDIO 0 4 1 45 V VREGIN_DIG 0 4 1 95 V O...

Страница 75: ...V 1 8V VDD_AUDIO_DRV 1 70 1 80 1 95 V VDD_AUX_1V8 1 70 1 80 1 95 V VDD_PADS_1 1 70 1 80 3 60 V VDD_PADS_2 1 70 1 80 3 60 V VDD_AUX_1V8 1 25 1 80 1 95 V 1 35V SMPS_1V35_SENSE 1 30 1 35 1 40 V VDD_AUDI...

Страница 76: ...stereo audio with 16 load a 25 mA Peak conversion efficiency b 90 Switching frequency 3 63 4 00 4 00 MHz Inductor saturation current stereo and 16 load 250 mA Inductor ESR 0 1 0 3 0 8 Low power Mode A...

Страница 77: ...00 MHz Inductor saturation current stereo and 16 load 400 mA Inductor ESR 0 1 0 3 0 8 Low power Mode Automatically Entered in Deep Sleep Transient settling time 200 s Load current 0 005 5 mA Current...

Страница 78: ...sient settling time 30 s Load current 160 mA Current available for external use stereo audio with 16 load 0 mA Peak conversion efficiency a 88 Switching frequency 3 63 4 00 4 00 MHz Inductor saturatio...

Страница 79: ...3 3 2 4 Low voltage VDD_ANA Linear Regulator Normal Operation Min Typ Max Unit Input voltage 1 70 1 80 1 95 V Output voltage 1 30 1 35 1 45 V Load current 60 mA 13 3 3 Regulator Enable VREGENABLE Swit...

Страница 80: ...Reduced headroom charge current as a percentage of Ifast I CTRL 0x0f headroom 0 15V 50 100 I CTRL charge current step size 5 mA Vfloat threshold calibrated 4 16 4 20 4 24 V Standby Mode Min Typ Max Un...

Страница 81: ...SB for correct USB operation 3 0 3 3 3 6 V Input Threshold VIL input logic level low 0 3 x 3V3_USB V VIH input logic level high 0 7 x 3V3_USB V Output Voltage Levels to Correctly Terminated USB Cable...

Страница 82: ...4 1kHz 88 dB 48kHz 88 dB THD N fin 1kHz B W 20Hz Fsample 2 20kHz max 1 6Vpk pk input Fsample 8kHz 0 0036 48kHz 0 0052 Digital gain Digital gain resolution 1 32 24 21 5 dB Analogue gain Pre amplifier s...

Страница 83: ...Hz 16 93 dB THD N fin 1kHz B W 20Hz 20kHz 0dBFS input Fsample Load 8kHz 100k 0 0019 8kHz 32 0 0024 8kHz 16 0 0032 48kHz 100k 0 0026 48kHz 32 0 0036 48kHz 16 0 0052 Digital Gain Digital Gain Resolution...

Страница 84: ...VOH output logic level high lOH 4 0mA 0 75 X VDD V Tr Tf 5 ns Input and Tristate Currents Strong pull up 150 40 10 A Strong pull down 10 40 150 A Weak pull up 5 1 0 0 33 A Weak pull down 0 33 1 0 5 0...

Страница 85: ...xiliary ADC Auxiliary ADC Min Typ Max Unit Resolution 10 Bits Input voltage range a 0 VDD_AUX V Accuracy Guaranteed monotonic INL 1 1 LSB DNL 0 1 LSB Offset 1 1 LSB Gain error 0 8 0 8 Input bandwidth...

Страница 86: ...oltage 1 30 1 35 1 40 V LSB size 0 1 32 2 64 mV Offset 1 32 0 1 32 mV Integral non linearity 1 0 1 LSB Settling time a 250 ns a The settling time does not include any capacitive load Advance Informati...

Страница 87: ...chine Model Contact Discharge per JEDEC EIA JESD22 A115 TBDV TBDV all pins except for RF and USB TBDV for RF pins TBDkV for USB_DP and USB_DN Charged Device Model Contact Discharge per JEDEC EIA JESD2...

Страница 88: ...bps No sniff TBD TBD TBD mA Slave Stereo high quality SBC 350kbps Sniff TBD TBD TBD mA Slave Stereo high quality MP3 128kbps No sniff TBD TBD TBD mA Slave Stereo high quality MP3 128kbps Sniff TBD TBD...

Страница 89: ...1280ms TBD mA Note Current consumption values are taken with VBAT pin 3 7V RF TX power set to 0dBm No RF retransmissions in case of eSCO Microphones and speakers disconnected with internal microphone...

Страница 90: ...sion 2009 251 EC Products containing dimethylfumarate DMF are not placed or made available on the market EU Packaging and Packaging Waste Directive 94 62 EC Montreal Protocol on substances that deplet...

Страница 91: ...yl Chloride PVC Banned Sulfur hexafluoride Banned Tetrachloromethane CAS 56 23 5 Banned Asbestos Banned as intentionally introduced Phthalates Banned as intentionally introduced Radioactive substances...

Страница 92: ...nd is easy to configure Most of the CSR8640 stereo headset ROM software features are configured on the CSR8640 BGA using the Headset Configurator tool The tool reads and writes headset configurations...

Страница 93: ...apable phone and an A2DP only source device e g a PC or an iPod touch The CSR8640 stereo headset enables Music streaming from either of the connected A2DP source devices where the music player is cont...

Страница 94: ...CSR8640 BGA includes CSR s proprietary mechanism for communicating with smartphone apps it enables full UI control of the headset from within the application running on a smartphone e g Google Android...

Страница 95: ...y reducing the audio processing performed by CVC at a series of low battery capacity thresholds Configurable IPM features include IPM enable disable The battery capacity that engages IPM A user action...

Страница 96: ...t 8 paired connected devices Using proximity connection means functions like power on into an incoming call operate equally well for the most recently paired or connected device as well as the least r...

Страница 97: ...on is a rules based filter which uses the 2 microphone s spatial information direction of arrival and power ratios assumptions etc Blind source separation results in speech S1 and noise S2 dominant ou...

Страница 98: ...s glitches referred to as pops and clicks in the audio stream The PLC block improves the receive path audio quality in the presence of bit and packet errors within the Bluetooth link by using a variet...

Страница 99: ...he adaptive equalisation module see Section 16 2 9 and the NDVC module see Section 16 2 12 to enhance intelligibility in the presence of noise This combination of functions creates higher frequency in...

Страница 100: ...points see Figure 16 4 Figure 16 4 Configurable EQ GUI with Drag Points Is configurable with up to 6 switchable bank presets This enables the headset user to select between the EQ bank presets through...

Страница 101: ...de DK 8640 10061 1A includes a CSR8640 stereo headset demonstrator board and necessary interface adapters and cables are available In conjunction with the CSR8640 stereo headset Configurator tool and...

Страница 102: ...ered Prototype Products designating them ES on the Quotation and any Order for Prototype Products shall be subject to the special terms contained in this clause 5 5 2 The Seller has used reasonable ef...

Страница 103: ...8 1 Tape Orientation 18 2 Tape Dimensions Figure 18 2 shows the dimensions of the tape for the CSR8640 BGA G TW 0007442 1 1 1 5 0 1 0 0 1 75 0 10 2 00 0 10 SEE NOTE 3 0 30 0 05 4 00 SEE NOTE 1 A A SEC...

Страница 104: ...0000386 3 2 Figure 18 3 Reel Dimensions Package Type Tape Width A Max B C D Min N Min W1 W2 Max W3 Units Min Max 5 5 x 5 5 x 1mm VFBGA 16 332 1 5 13 0 0 5 0 2 20 2 50 16 4 3 0 0 2 19 1 16 4 19 1 mm 18...

Страница 105: ...d Labelling Specification CS 112584 SP Kalimba Architecture 3 DSP User Guide CS 202067 UG Lithium Polymer Battery Charger Calibration and Operation for CSR8670 CS 204572 AN Moisture Reflow Sensitivity...

Страница 106: ...Audio Video Remote Control Profile BCCMD BlueCore Command BCSP BlueCore Serial Protocol BEC Bit Error Concealment BER Bit Error Rate BFI Bad Frame Indicator BIST Built In Self Test BlueCore Group term...

Страница 107: ...c Industries Alliance EQ EQualiser eSCO Extended SCO ESD Electrostatic Discharge ESR Equivalent Series Resistance etc et cetera and the rest and so forth FIR Finite Impulse Response filter FSK Frequen...

Страница 108: ...ssociation Kalimba An open platform DSP co processor enabling support of enhanced audio applications such as echo and noise suppression and file compression decompression Kb Kilobit LC An inductor L a...

Страница 109: ...LC Packet Loss Concealment plc Public Limited Company PS Key Persistent Store Key PWM Pulse Width Modulation RAM Random Access Memory RC A Resistor and Capacitor network RF Radio Frequency RGB Red Gre...

Страница 110: ...rface SPP Serial Port Profile TBD To Be Defined THD N Total Harmonic Distortion and Noise TX Transmit or Transmitter UART Universal Asynchronous Receiver Transmitter UI User Interface USB Universal Se...

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