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IQ–P.I.P.–SLM Programmable Input Processor with Load Monitoring for IQ Systems
Reference Manual
5 Technical Information
The purpose of the
IQ–P.I.P.–SLM is to provide remote
control and monitoring of a PIP2-compatible amplifier.
In addition, the
IQ–P.I.P.–SLM provides Load Monitor-
ing functions which allow storage of amplifier voltage
(frequency response) and load impedance curves.
See Sections 1 and 2 for a detailed description of fea-
tures and facilities. Figure 5.1 on the following page
shows the block diagram of the unit.
5.1 Audio Signals
Audio enters the
IQ–P.I.P.–SLM through the dual 3-pin
Eurostyle barrier block connectors. The signal is RFI
filtered and converted from balanced to single-ended.
From this point, audio is passed through a routing
switch, which connects either the incoming audio or
the signal generator to the stages that follow. The sig-
nal then is fed to a digitally controlled analog attenua-
tor, which provides level control and muting. At this
stage, the signal is also split off and sent to the A/D
converter, which is used to report input signal levels
via the IQ bus. Following the attenuator, the signal
passes through a final output buffer which also can in-
vert the signal polarity under microprocessor control.
The audio signal is then fed through the PIP2 ribbon
cable to the amplifier.
5.2 Amplifier Monitoring
The
IQ–P.I.P.–SLM can monitor the status of the ampli-
fier using a variety of monitor inputs, obtained from two
basic signal types: audio and status.
Audio signals which are monitored include input level
to P.I.P., output voltage of amplifier, and output current
of amplifier. The signals enter the P.I.P., are buffered,
level-shifted, and sent to an A/D converter. The con-
verter samples the signals and converts them to a form
suitable for use by the
IQ System. The conversion in-
cludes averaging, peak hold, and log functions.
Status signals which are monitored include ODEP
Level (thermodynamic headroom), IOC Indicators,
AUX input, and amplifier fault status. The signals enter
the P.I.P. and are sent to the microprocessor through
and A/D converter or logic input. The microprocessor
then converts the signals to a form suitable for use by
the
IQ System.
5.3 Amplifier Control
The
IQ–P.I.P.–SLM can control the following functions:
high-voltage supplies on/off, audio input level (0 to
–80 dB in 0.5-dB steps), audio polarity, DATA LED, and
AUX output. These functions are controlled using ports
on the microprocessor and some external support cir-
cuitry. The audio level is controlled by the micropro-
cessor through a digitally controlled analog attenuator.
The data LED flashes for 10 mS whenever a valid IQ
command is received by the P.I.P.
5.4 Signal Generator
Test signals are generated using direct digital synthe-
sis. The DDS chip is controlled by the microprocessor
and the audio output of the generator is switched into
the signal path with digitally controlled analog
switches.
5.5
IQ System Communications
The
IQ–P.I.P.–SLM communicates with the host com-
puter via the Crown Bus. Connections to the Crown Bus
are made via the 4-pin removable Eurostyle barrier
block connector on the rear panel. IQ commands en-
tering the
P.I.P. are fed into an input receiver circuit that
converts the 20 mA current loop signal into a standard
logic signal that the microprocessor can understand.
This signal is also passed directly to the Crown Bus for
output where it is passed on to the remainder of the
loop. Data sent in response to IQ commands is also
sent through the Crown Bus output where it passes
through the remainder of the loop and back to the host
computer. A “drop out” relay is also present which
makes a physical contact between the Crown Bus in-
put and output connectors in the event of a power fail-
ure. This means that as long as the Crown Bus cables
are connected to the
P.I.P., the Crown Bus will remain
unbroken—even if power to the
P.I.P. is lost.
5.6 Microprocessor, Digital Logic,
and Reset Switch
The “brains” of the
IQ–P.I.P.–SLM are contained in the
microprocessor. It interprets commands received from
the Crown Bus and responds accordingly. The micro-
processor also interfaces with several support compo-
nents, including RAM, EEPROM, an A/D converter,
memory decode, and data latches. The reset switch is
connected to the microprocessor and generates an
interrupt when pressed. Depending on how long the
switch is held, the system resets with either factory de-
fault (>2 seconds) or user preset operating parameters
(<2 seconds).