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KIT8020CRD8FF1217P-1_UM Rev -
User Manual
Figure 1. General block diagram of Cree Discrete SiC EVL board
Please note that JM1 as shown in Figure 1 is open circuit. It is
necessary to short this with a wire or insert a shunt as shown in
section 6.2 to complete the circuit before operation.
CRD8FF1217P-1 includes two 2.5A gate driver integrating opto-coupler from Avago
ACPL-W346 and two 2W isolation DC/DC converters from Mornsun G1212S-2W for
both high side and low side isolated power. The 2W DC/DC converter with +12V Vcc
input gen24V Vcc_out output voltage with 6KVDC isolation that is supplying
voltage to W346 on push-pull gate drive of the secondary side as shown in Figure 2.
In this circuit, a 5V zener in parallel with 1uF capacitor is used to generate -5V Vgs
voltage for the SiC MOSFET turn-off and turn-on Vgs voltage is equal to 24V-5V=19V.
Note that SiC MOSFET can be turned off with zero voltage, and the -5V turn-off
voltage helps with faster turn-off and lower turn-off losses and also improves dv/dt
induced self turn-on and noise immunity during transient periods with more margin for
Vgs turn-on threshold voltage. You can implement any PWM signal to drive the SiC
phase leg block, if the board is operating in synchronous mode with high side
MOSFET and low side MOSFET, the input signals must have additional dead time to
avoid shoot through.
CON1
CON3
CON2
CON5
CON4
CRD8FF1217P-1
VCC, Input PWM Signal,
Enable
SiC
Phase-leg
block
ACPL-W346
DC/DC
ACPL-W346
DC/DC
Vcc
Vcc
Vcc_out
Vcc_out
Vg_HS
Vg_LS
HS_I/P
LS_I/P
5V
5V
Vs_LS
Vs_LS
Figure 2. CRD8FF1217P-1 Block diagram with ACPL-W346
