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Xtreme I/O Express ADC-DAC   

Users Guide 

www.connecttech.com

 

 

Document: CTIM-00435 
Revision: 0.08 

 

 

Page 14 of 47 

Connect Tech Inc.  800-426-8979 | 519-836-1291

 

Date: 2016-11-18 

 

 

 

Operation 

 
The ADCs are controlled and have their data stored in four  controller blocks. The mode of capture 
can be set to either 

Continuous Sampling Mode 

or 

Waveform Capture Mode

.  The input range for 

each of the 4 ADCs can be changed via the INPUT_RANGE_SELECT register. 
 
Each ADC block can be set to capture up to 8 channels in a looping sequential order.  For example, if 
all eight channels were enabled in ADC0 (writing 0xFF to CONTROL_CONFIG) then the following 
shows the process it would go through in obtaining the requested samples:  
 

 

 
By default sample collection occurs at the maximum sampling rate of the ADC IC which is 500ksps, 
so if, in continuing the previous example, all 8 channels were to be enabled then the actual sampling 
rate per ADC Channel would be 500ksps/8=62.5ksps. 
 
 

Continuous Sampling Mode

 

Each ADC channel’s code is captured and stored into their CHX-LAST_SAMPLE register.  This 
CHX-LAST_SAMPLE register is then constantly updated/overwritten with a latest/newest code 
received. 
  

Waveform Capture Mode (FIFO Mode) 

This mode is supplementary to the Continuous Sampling Mode in that the ADC blocks will continue 
to update their CHX-LAST_SAMPLE registers while also storing data in their associated sample 
FIFOs.   
 
An ADC block operating in this mode will signal that its FIFO memory is almost full via a PCIe 
interrupt; the sample count at which this notification is made can be adjusted to any value within the 
sample depth range supported by the sample FIFOs (2046).  Each sample is stored in the FIFOs is 
saved along with two additional bookkeeping data fields: the channel number and the sample number. 
 

31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

11-bit "Timestamp"/Sample Num 

R 

Channel ID 

16-bit CODE from ADC 

 
 
For example to set up an ADC block to capture data in its sample FIFO and provide a notification 
once it has stored 1023 of these values, one would write 0x3FF to the first ten bits of its 
MEM_WRITE_CONTROL register and then set the MEM Store flag in its CONTROL_CONFIG 
register.  
 
 

Variable Sampling Rate

 

As already touched upon the default sampling rate of the ADC blocks is 500ksps or the maximum rate 
supported by the ADC peripherals.  If slower sampling rates are required, then each block can be 
individually set to subdivide this maximum rate by way of a counter roll over value stored in the 
CLK_DIV_CNTR register.   
 

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Содержание DAG103

Страница 1: ...eme I O Express ADC DAC Connect Tech Inc Tel 519 836 1291 42 Arrow Road Toll 800 426 8979 North America only Guelph Ontario Fax 519 836 4878 N1K 1S6 Email sales connecttech com www connecttech com support connecttech com CTIM 00435 Revision 0 08 2016 11 18 ...

Страница 2: ... Our support section is available 24 hours a day 7 days a week on our website at www connecttech com sub support support asp See the contact information section below for more information on how to contact us directly Our technical support is always free Contact Information Mail Courier Connect Tech Inc Technical Support 42 Arrow Road Guelph Ontario Canada N1K 1S6 Email Internet sales connecttech ...

Страница 3: ...Product returned to Connect Tech Inc must be pre authorized by Connect Tech Inc with an RMA Return Material Authorization number marked on the outside of the package and sent prepaid insured and packaged for safe shipment Connect Tech Inc will return this product by prepaid ground shipment service The Connect Tech Inc Limited Warranty is only valid over the serviceable life of the product This is ...

Страница 4: ...t as the property of their respective owners Not listing all possible trademarks or copyright acknowledgments does not constitute a lack of acknowledgment to the rightful owners of the trademarks and copyrights mentioned in this document ESD Warning Electronic components and circuits are sensitive to ElectroStatic Discharge ESD When handling any circuit board assemblies including Connect Tech COM ...

Страница 5: ...reated 0 02 2015 02 19 Updated with Core Content 0 03 2015 05 14 Updated to reflect new firmware revision 0 04 2015 05 19 Finished Signal Gen Section 0 05 2015 05 25 Finished PWM Section 0 06 2016 06 22 Updated photos and warranty policy 0 07 2016 07 18 Updated overall manual format and organization Revised information on PWM controller interrupt controller common board features Add C code example...

Страница 6: ...ard Operation 12 Analog Inputs ADC s 13 Overview 13 Connectors Jumpers 13 Operation 14 Memory Map 15 Register Details 16 CONTROL_CONFIG ADC Offset 0x0000 Read Write 16 INPUT_RANGE_SELECT ADC Offset 0x0010 Read Write 16 CHx_LAST_SAMPLE Offset 0x0014 Read Only 16 MEM_WRITE_CONTROL ADC Offset 0x0024 Read Write Partial 18 Application Examples 18 Example A ADC Operation with same input range 18 Example...

Страница 7: ...xample C Sine wave generation 32 GPIO Digital I O 34 Overview 34 Connectors Jumpers 34 Operation 35 Memory Map 35 Register Details 35 GPIO_INPUT Offset 0x0000 Read Only 35 GPIO_OUTPUT Offset 0x0004 Read Write 36 GPIO_CMD Offset 0x0008 Read Write 36 Application Examples 36 Example A Walking 1 s and 0 s 36 Flash Controller 38 Overview 38 Operation 38 Memory Map 38 Register Details 38 Common Features...

Страница 8: ...to 5V 0V to 10V Bipolar 5V 10V 2 5V 2 5V to 7 5V Accuracy 1LSB INL and DNL Settling Time 6µs Outputs Drive 3mA Digital I O Channels 16 bit bidirectional I O Input Output Ranges Hardware selectable 3 3V or 5V TTL CMOS Output Drive High Current 24mA Controller FPGA Register Controlled Device No jumpers needed Custom logic available upon request Operating Temperature 40 to 85 Degrees Celsius Dimensio...

Страница 9: ...g Outputs 16 bit 4 Channels GPIO 16 bits DAG104 Analog Inputs 16 bit 32 SE Analog Outputs none GPIO 16 bits DAG106 Analog Inputs 16 bit 32 SE Analog Outputs 16 bit 4 Channels GPIO 16 bits Humiseal 1B31 Conformal Coating To order any of these part numbers or to inquire about the other available ordering options please contact sales connecttech com for further information ...

Страница 10: ... 1291 Date 2016 11 18 Product Overview The Xtreme I O Express ADC DAC is based on a custom FPGA controller SPI ADCs and DAC s The following block diagram shows the connection between the interfaces Each SPI bus is independent and managed by separate control block Connection to analog signals are provided by two standard connectors Block Diagram ...

Страница 11: ... 519 836 1291 Date 2016 11 18 Connector Summary Locations Designator Description P1 JTAG Programming P2 P5 PCIe 104 Connector P3 General Purpose Inputs and Outputs P4 Analog Inputs P5 JTAG programming P7 Analog Outputs P8 PCI 104 Connector Jumper Summary Locations Designator Description J2 General Purpose Input and Output Voltage Level ...

Страница 12: ...IO controller interrupt controller on board flash programming controller and board identification Offset Identifier Description 0x0000 COMMON_BASE General Board control 0x1000 ADC0 Analog to Digital Controller 0 0x4000 ADC1 Analog to Digital Controller 1 0x7000 ADC2 Analog to Digital Controller 2 0xA000 ADC3 Analog to Digital Controller 3 0xD000 DAC Digital to Analog Controller 0x10000 GPIO_BASE G...

Страница 13: ...r The ADC IC datasheet can be found here http www ti com lit gpn ads8688 Connectors Jumpers Function Analog Inputs Location P4 Type Samtec HTSW 120 08 L D RA 2x20 0 100 pitch Mate Any 0 100 cable Pinout Pin Description Pin Description 1 ADC0 CH 0 2 ADC0 CH 1 3 ADC0 CH 2 4 ADC0 CH 3 5 ADC0 CH 4 6 ADC0 CH 5 7 ADC0 CH 6 8 ADC0 CH 7 9 GND 10 GND 11 ADC1 CH 0 12 ADC1 CH 1 13 ADC1 CH 2 14 ADC1 CH 3 15 A...

Страница 14: ...FO Mode This mode is supplementary to the Continuous Sampling Mode in that the ADC blocks will continue to update their CHX LAST_SAMPLE registers while also storing data in their associated sample FIFOs An ADC block operating in this mode will signal that its FIFO memory is almost full via a PCIe interrupt the sample count at which this notification is made can be adjusted to any value within the ...

Страница 15: ...by storing new values only when the counter is equal to zero Memory Map The following register offsets are from each ADC block offset Example ADC1 CONTROL_CONFIG Offset Hex 0x03 0x02 0x01 0x00 setup config 0x0000 CONTROL_CONFIG 0x0004 STATUS 0x0008 CLK_DIV 0x000C CLK_DIV_CNTR 0x0010 INPUT_RANGE_SELECT last samples 0x0014 CH1 LAST_SAMPLE CH0 LAST_SAMPLE 0x0018 CH3 LAST_SAMPLE CH2 LAST_SAMPLE 0x001C...

Страница 16: ...1 10 9 8 7 6 5 4 3 2 1 0 Reserved CH7 Range CH6 Range CH5 Range CH4 Range CH3 Range CH2 Range CH1 Range CH0 Range This register contains all of the channel input range values which are described below CHx Range 2 0 Postive Full Scale V Negative Full Scale V Full Scale Range V LSB µV 000 10 24 10 24 20 48 312 5 001 5 12 5 12 10 24 156 25 010 2 56 2 56 5 12 78 125 101 10 24 0 10 24 156 25 110 5 12 0...

Страница 17: ...800 426 8979 519 836 1291 Date 2016 11 18 Code translation examples Code CHx Range 2 0 FSR Actual Voltage Graph 0x0000 000 20 48V 10 24V 0x8000 000 20 48V 0 00V 0xffff 000 20 48V 10 24V 0x0000 001 10 24V 5 12V 0x8000 001 10 24V 0 00V 0xffff 001 10 24V 5 12V 0x0000 110 5 12V 0 00V 0x8000 110 5 12V 2 56V 0xffff 110 5 12V 5 12V ...

Страница 18: ...UFD and API Example A ADC Operation with same input range In this example we will set the 2 ADC IC s to enable sampling and set the input range for each of the ADCs to be 10 24V Then we will read back all the channels printf ADC0 1 enabling chan0 7 and setting input range n control_config 0xFF CTIFPGAWrWord pbrd BarIndex ADC0 CONTROL_CONFIG control_config CTIFPGAWrWord pbrd BarIndex ADC1 CONTROL_C...

Страница 19: ...ol_config CTIFPGAWrWord pbrd BarIndex ADC1 CONTROL_CONFIG control_config input_range 0x0 CTIFPGAWrDword pbrd BarIndex ADC0 INPUT_RANGE_SELECT input_range input_range 0x0 for ch 0 ch 8 ch input_range 0x5 3 ch CTIFPGAWrDword pbrd BarIndex ADC1 INPUT_RANGE_SELECT input_range printf nReading ADC Voltages n i 0 CTIFPGARdWord pbrd BarIndex ADC0 CH0_LAST_SAMPLE i 2 testreg ADC0votlage testreg 20 48 0x100...

Страница 20: ...ppropriate bits in the TRG_SIGGEN_PWM register Direct Write Mode In this mode the DAC controller responds to writes to the CH0_DATA CH1_DATA CH2_DATA CH3_DATA registers and then immediately sends the contents of one or the other if it detects a write has been made A write to CH0_DATA will trigger the transmission of the new values to channel 0 and 1 and a write to address CH2_DATA will trigger the...

Страница 21: ...generate a square wave of variable period between two specified analog values The waveform is controlled by PWM_HIGH_COUNT and PWM_LOW_COUNT registers represent the number of clock cycles in which the pulse will remain high and low The count values are passed to the pulse generator unit switching between counting up to the high and low values from 0 and toggling the analog output between the value...

Страница 22: ...Cx_CODE in Two s Complement Code for Bipolar Output Operation Note Gain 4 Vref 5 DACx_CODE in Straight Binary Code for Unipolar Output Operation Note Vref 5 Note saturation point will be at 15V so actually highest code will be 0xC000 DAC8734 Internal DACx Zero Code The Zero Register stores the user calibration data that are used to eliminate the offset error The data are nine bits wide 0 125 LSB s...

Страница 23: ...36 1291 Date 2016 11 18 The Gain Register stores the user calibration data that are used to eliminate the gain error The data are eight bits wide 1 LSB step and the total adjustment is typically 128 LSB to 127 LSB or 0 195 of full scale range The Gain Register uses a twos complement data format in both bipolar and unipolar modes of operation ...

Страница 24: ...28 SIG_GEN_RD_CTRL 0x002C PWM_HIGH_COUNT PWM_LOW_COUNT 0x0030 PWM_FREQ_FAC PWM_CTRL 0x0034 PWM_HIGH_VAL PWM_LOW_VAL 0x0038 SAMPLE_DIV_CNTR mem block 0x1000 SIG_GEN_MEM_0 0x1004 0x2FFC Register Details DCONTROL_CONFIG Offset 0x0000 Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Future Use Configuration This registers holds the value that wi...

Страница 25: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Future Use CH0_ZERO CH0_GAIN CH0_ZERO stores user calibration data that is used to eliminate offset error CH0_GAIN stores user calibration data that is used to eliminate gain error CH1_ZERO CH1_GAIN Offset 0x0010 Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Страница 26: ...8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Future Use UB UA RST LD This register sets the Unipolar and Bipolar modes of the outputs for each group of DAC outputs It is unique among all the other registers in that it is actually a direct mapping to pins on the peripheral bearing the same designations UB 0 Sets DAC2 DAC3 to Bipolar Mode 10V to 10V 1 Sets DAC...

Страница 27: ...are undefined do not load any values other than 0x3C into this location 0x4 DAC0 CODE This register contains the 16 bit code for the specific DAC output 0 1 2 or 3 Bit 15 MSB Bit 0 LSB CODE Formats For UNIPOLAR Mode Straight Binary For BIPOLAR Mode Two s Complement 0x5 DAC1 CODE Same as DAC0 CODE 0x6 DAC2 CODE Same as DAC0 CODE 0x7 DAC3 CODE Same as DAC0 CODE 0x8 DAC0 ZERO CODE 0x9 DAC1 ZERO CODE ...

Страница 28: ...GEN_PWM BASE_MEM_ADDR Memory address containing the first encoded voltage level of the signal to be output READ_COUNT Length of the signal to be output effectively then the address of the last voltage level output is Base Memory Address Read Count CHAN Channel to send generated signal output to D Use SAMPLE_DIV_CNTR value to subdivide the output frequency of the generated signal PWM_LOW_COUNT PWM_...

Страница 29: ...division PWM_CTRL E 1 Enable the pulse generator 0 Disable the pulse generator either bit can be used to support older s w R 1 Reset the pulse generator 0 normal operation PWM_HIGH_VAL PWM_LOW_VAL Offset 0x0034 Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_HIGH_VAL PWM_LOW_VAL PWM_HIGH_VAL The DAC code to output when the PWM signal is output a...

Страница 30: ...2_DATA 0xC000 16 0x8000 Example B PWM Setup define BOARD_GAIN 4 define BOARD_VREF 5 define CLK 102000000 void pwmSetup CtiUfpgaBoard pbrd U8 BarIndex U16 lowcnt U16 highcnt U8 freqMult U16 highCode U16 lowCode U32 pwmCnt pwmCtrl pwmLvl siggen rb float freq float period Disable Output PWM siggen 0x0 CTIFPGAWrDword pbrd BarIndex DAC0 TRG_SIGGEN_PWM siggen Setting pwm cycle period float lowcnt highcn...

Страница 31: ...ADC DAC Users Guide www connecttech com Document CTIM 00435 Revision 0 08 Page 31 of 47 Connect Tech Inc 800 426 8979 519 836 1291 Date 2016 11 18 siggen 0x3 CTIFPGAWrDword pbrd BarIndex DAC0 TRG_SIGGEN_PWM siggen return ...

Страница 32: ...mples i 65536 2 BOARD_GAIN BOARD_VREF else codeList i samples i 65536 2 BOARD_GAIN BOARD_VREF currentPhase phaseIncrement U8 dacWave CtiUfpgaBoard pbrd U8 result TRUE unsigned int i addr U8 unipolar U16 dacCode TABLE_SIZE U32 wrCode rdCode ctrl divcntr siggen i 0 Setup all DAC siggen 0x0 CTIFPGAWrDword pbrd BarIndex DAC0 TRG_SIGGEN_PWM siggen load the array with a sinewave see above function genSi...

Страница 33: ...pbrd BarIndex DAC0 SIG_GEN_MEM_0 i 4 rdCode if wrCode rdCode printf error d read x wrote x i rdCode wrCode load the control registers channel 0 2047 count start at offset 0 ctrl 0 24 ctrl 0x0 22 ctrl 0x7FF DAC_MEM_DWORDS 1 11 ctrl 0x0 CTIFPGAWrDword pbrd BarIndex DAC0 SIG_GEN_RD_CTRL ctrl divcntr 2 CTIFPGAWrDword pbrd BarIndex DAC0 SAMPLE_DIV_CNTR divcntr enable the signal genarator siggen 0x2 CTI...

Страница 34: ...IO8 GPIO15 upper can be set to either inputs or outputs independently Connectors Jumpers Function General Purpose I O Location P7 Type Samtec HTSW 113 08 G D RA 2x13 0 100 pitch Mate Any 0 100 cable Pinout Pin Description Pin Description 1 GPIO0 2 GPIO1 3 GPIO2 4 GPIO3 5 GPIO4 6 GPIO5 7 GPIO6 8 GPIO7 9 GPIO8 10 GPIO9 11 GPIO10 12 GPIO11 13 GPIO12 14 GPIO13 15 GPIO14 16 GPIO15 17 GND 18 GND 19 GND ...

Страница 35: ...s register memory offsets from the start of the GPIO block i e GPIO_BASE GPIO_INPUT Offset Hex 0x03 0x02 0x01 0x00 0x0000 GPIO_INPUT 0x0004 GPIO_OUTPUT 0x0008 GPIO_CMD Register Details GPIO_INPUT Offset 0x0000 Read Only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Future Use Upper Byte GPIO Pins Lower Byte GPIO Pins This register contains the state...

Страница 36: ...t to be low GPIO_CMD Offset 0x0008 Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Future Use UB LB UB 0 GPIO Pins 8 to 15 are set to OUTPUTS 1 GPIO Pins 8 to 15 are set to INPUTS LB 0 GPIO Pins 0 to 7 are set to OUTPUTS 1 GPIO Pins 0 to 7 are set to INPUTS Application Examples Example A Walking 1 s and 0 s printf Setting Direction Upper By...

Страница 37: ...ech Inc 800 426 8979 519 836 1291 Date 2016 11 18 for count 0 count 8 count CTIFPGAWrByte pbrd BarIndex GPIO_BASE GPIO_OUTPUT 0x1 outgpio CTIFPGARdByte pbrd BarIndex GPIO_BASE GPIO_INPUT ingpio Compare Values if outgpio ingpio printf ERROR MIS MATCH n result FALSE else printf OK n Shift the 0 over outgpio outgpio 1 1 ...

Страница 38: ...GA is not update until the next power cycle Update flash and liver reconfiguration the flash is erased and new configuration image is written then verified The PCIe configuration registers are then save the a configuration cycle is initiated and the PCIe configuration registers are restored Operation For futher details on the flash controller operation contact support connecttech com to obtain the...

Страница 39: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not used D A C A D C 3 A D C 2 A D C 1 A D C 0 ADC0 ADC controller block 0 has a FIFO over the trigger level ADC1 ADC controller block 1 has a FIFO over the trigger level ADC2 ADC controller block 2 has a FIFO over the trigger level ADC3 ADC controller block 3 has a FIFO over the trigger level DAC ADC controller block The register must be written t...

Страница 40: ...2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not used F L A S H D A C A D C 3 A D C 2 A D C 1 A D C 0 ADC0 ADC controller block 0 has a pending interrupt ADC1 ADC controller block 1 has a pending interrupt ADC2 ADC controller block 2 has a pending interrupt ADC3 ADC controller block 3 has a pending interrupt DAC DAC controller block has a pending interrupt FLASH SPI Flash controller b...

Страница 41: ...This is the overall interrupt enable for each functional block To mask an interrupt set the bit to 0 RELEASE ID_BASE 0x0 Read Only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Board ID 0x12C4 Release Version 0x6 TIMESTAMP ID_BASE 0x4 Read Only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Timestamp see software applic...

Страница 42: ...registers printf reading ID registers n time_t rawtime struct tm timeinfo ret CTIFPGARdDword pbrd BAR_MAIN ID_BASE 0x0 idreg if ret CTI_STATUS_OK printf Error read from FPGA mem result FALSE else printf ID reg 0x 08x n idreg ret CTIFPGARdDword pbrd BAR_MAIN ID_BASE 0x4 tsreg if ret CTI_STATUS_OK printf Error read from FPGA mem result FALSE else rawtime tsreg timeinfo localtime rawtime printf Times...

Страница 43: ...3 of 47 Connect Tech Inc 800 426 8979 519 836 1291 Date 2016 11 18 PCIE 104 Interface The below table details the pinout of the PCIe 104 connector and what pins signals are used on the Xtreme I O Express ADC DAC Note this product only uses the 5V rail power connection and a single x1 PCI Express Link ...

Страница 44: ... NC Pass Thru 71 73 GND GND 74 74 GND GND 73 75 NC Pass Thru NC Pass Thru 76 76 NC Pass Thru NC Pass Thru 75 77 NC Pass Thru NC Pass Thru 78 78 NC Pass Thru NC Pass Thru 77 79 GND GND 80 80 GND GND 79 81 NC Pass Thru NC Pass Thru 82 82 NC Pass Thru NC Pass Thru 81 83 NC Pass Thru NC Pass Thru 84 84 NC Pass Thru NC Pass Thru 83 85 GND GND 86 86 GND GND 85 87 NC Pass Thru NC Pass Thru 88 88 NC Pass ...

Страница 45: ...t the Xtreme I O Express ADC DAC onto PCI 104 Express stack clip into place depending on the available mounting hardware 3 Attached the application cabling to the analog input connector analog output connector and GPIO connector 4 Set the GPIO voltage level jumper to as required for the application 5 Power on the system 6 Under Linux use lspci vvt to verify the presence of the Mini PCIe ADC The Ve...

Страница 46: ...0x14 2 define CH2_LAST_SAMPLE 0x18 define CH3_LAST_SAMPLE 0x18 2 define CH4_LAST_SAMPLE 0x1C define CH5_LAST_SAMPLE 0x1C 2 define CH6_LAST_SAMPLE 0x20 define CH7_LAST_SAMPLE 0x20 2 define MEM_WR_CONTROL 0x24 define MEM_SAMPLE_0 0x1000 define CH_ID_TIMESTAMP_0 0x1000 2 define CH_ID_TIMESTAMP_4k 0x2FFC 2 define DAC0 0xD000 define DAC0 0x4000 for reduced version define DCONTROL_CONFIG 0x00 define CH0...

Страница 47: ...PWM_LOW_VAL 0x34 define PWM_HIGH_VAL 0x36 define SAMPLE_DIV_CNTR 0x38 define SIG_GEN_MEM_0 0x1000 define SIG_GEN_MEM_4K define GPIO_BASE 0x10000 define GPIO_INPUT 0x0 define GPIO_OUTPUT 0x4 define GPIO_CMD 0x8 define FLASH_BASE 0x24000 define SPI_CMD 0x0000 define SPI_PARAM 0x0004 define SPI_STATUS 0x0008 define SPI_RESULT 0x000C define SPI_PAGE_MEM 0x0100 define ID_BASE 0x24210 define RELEASE 0x0...

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