Copyright
©
2016
congatec
AG
TSSLm11.indd
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Feature
Options
Description
Program PCIe ASPM after
OpROM
Disabled
Enabled
‘Enabled’ - PCIe ASPM will be programmed after OpROM.
‘Disabled’ - PCIe ASPM will be programmed before OpROM.
Program Static Phase1 Eq
Disabled
Enabled
Program Phase1 Presets/CTLEp.
►
Gen3 Root Port Preset Value
for each Lane
Submenu
In this submenu, the root port preset value for PEG port lanes 0 -15 can be set individually.
►
Gen3 Endpoint Preset Value
for each Lane
Submenu
In this submenu the endpoint preset value for PEG port lanes 0 -15 can be set individually.
►
Gen3 Endpoint Hint Value
for each Lane
Submenu
In this submenu the endpoint hint value for PEG port lanes 0 -15 can be set individually.
►
Gen3 RxCTLE Control
Submenu
In this submenu, the RxCTLE Value for PEG bundle (lanes 0,1 - 14,15) can be set individually.
Gen3 Adaptive Software Equalization
Always Attempt SW EQ
Enabled
Disabled
Enable to always attempt SW EQ, even it has been done once.
Number of Presets to test
Auto
0-9
7, 3, 5
‘Auto’ - Recommended by Intel
®
.
SW EQ Enable VOC
Auto
Jitter & VOC Test Mode
Jitter Only Test Mode
Select Jitter and VOC test mode (default) or Jitter only test mode.
‘Auto’ will select Jitter and VOC test mode.
Jitter Dwell Time
3000
0-65535
Set PEG Gen3 preset search dwell time in [ms].
Jitter Error Target
2
0-65535
Set margin search error target value.
VOC Dwell Time
10000
0-65535
Set VOC dwll time in [usec].
VOC Error Target
2
0-65535
Set VOC margin search error target value.
Generate BDAT PEG Margin
Data
Enabled
Disabled
Enable or disable PEG generate BDAT margin table.
PCIe Rx CEM Test Mode
Disabled
Enabled
Enable or disable the PEG Rx CEM Loopback Mode.
11.4.22 UEFI Network Stack Submenu
Feature
Options
Description
UEFI Network Stack
Disabled
Enabled
Enable or disable the UEFI network stack.
