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8.4.18 PCI Express GEN 2 Settings Submenu
Feature Options Description
PCI Express GEN2 Device Register Settings
Completion Timeout
Default
Shorter
Longer
Disable
In device Functions that support Completion Timeout programmability, allows system software to modify the Completion
Timeout value. 'Default' 50us to 50ms. If 'Shorter' is selected, software will use shorter timeout ranges supported by
hardware. If 'Longer' is selected, software will use longer timeout ranges.
ARI Forwarding Disabled
Enabled
If supported by hardware and set to 'Enabled', the Downstream Port disables its traditional Device Number field being
0 enforcement when turning a Type1 Configuration Request into a Type0 Configuration Request, permitting access to
Extended Functions in an ARI Device immediately below the Port. Default value: Disabled
AtomicOp Requester
Enable Disabled
Enabled
If supported by hardware and set to 'Enabled', this function initiates AtomicOp Requests only if Bus Master Enable bit is
in the Command Register Set.
AtomicOp Egress Blocking Disabled
Enabled
If supported by hardware and set to 'Enabled', outbound AtomicOp Requests via Egress Ports will be blocked.
IDO Request Enable Disabled
Enabled
If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit
(Attribute[2]) requests to be initiated.
IDO Completion Enable Disabled
Enabled
If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit
(Attribute[2]) requests to be initiated.
LTR Mechanism Enable Disabled
Enabled
If supported by hardware and set to 'Enabled', this enables the Latency Tolerance Reporting (LTR) Mechanism.
End-End TLP Prefix
Blocking
Disabled
Enabled
If supported by hardware and set to 'Force to 2.5 GT/s' for Downstream Ports, this sets an upper limit on Link operational
speed by restricting the values advertised by the Upstream component in its training sequences. When 'Auto' is selected
HW initialized data will be used.
PCI Express GEN2 Link Register Settings
Target Link Speed
Auto
Force to 2.5 GT/s
Force to 5.0 GT/s
If supported by hardware and set to 'Force to 2.5 GT/s' for Downstream Ports, this sets an upper limit on Link operational
speed by restricting the values advertised by the Upstream component in its training sequences. When 'Auto' is selected
HW initialized data will be used.
Clock Power Management Disabled
Enabled
If supported by hardware and set to 'Enabled', the device is permitted to use CLKREQ# signal for power management of
Link clock in accordance to protocol defined in appropriate form factor specification.
Compliance SOS Disabled
Enabled
If supported by hardware and set to 'Enabled', this will force LTSSM to send SKP Ordered Sets between sequences when
sending Compliance Pattern or Modified Compliance Pattern.
Hardware Autonomous
Width
Disabled
Enabled
If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link width except width
size reduction for the purpose of correcting unstable link operation.
Hardware Autonomous
Speed Disabled
Enabled
If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link speed except speed
rate reduction for the purpose of correcting unstable link operation.