Copyright
©
2013
congatec
AG
TU87m12
73/114
10.2
PCI Configuration Space Map
Table 31 PCI Configuration Space Map
Bus Number (hex) Device Number (hex)
Function Number (hex) Description
00h
00h
00h
Host Bridge
00h
02h
00h
Graphics
00h
03h
00h
Intel High Definition Audio controller
00h
14h
00h
XHCI Host Controller
00h( Note1)
16h
00h
Management Engine (ME) Interface 1
00h( Note1)
16h
01h
Intel ME Interface 2
00h( Note1)
16h
02h
ME IDE Redirection (IDE-R) Interface
00h( Note1)
16h
03h
ME KT (Remote Keyboard and Text)
00h
19h
00h
Onboard Gigabit LAN Controller
00h (Note2)
1Ch
00h
PCI Express Root Port 0
00h (Note2)
1Ch
01h
PCI Express Root Port 1
00h (Note2)
1Ch
02h
PCI Express Root Port 2
00h (Note2)
1Ch
03h
PCI Express Root Port 3
00h
1Dh
00h
EHCI Host Controller
00h
1Fh
00h
PCI to LPC Bridge
00h
1Fh
02h
Serial ATA Controller
00h
1Fh
03h
SMBus Host Controller
00h
1Fh
06h
Thermal Subsystem
01h (Note3)
00h
00h
PCI Express Port 0
02h (Note3)
00h
00h
PCI Express Port 1
03h (Note3)
00h
00h
PCI Express Port 2
04h (Note3)
00h
00h
PCI Express Port 3
Note
1.
In the standard configuration, the Intel Management Engine (ME) related devices are partly present or not present at all.
2. The PCI Express Ports are visible only if a device is attached behind them to the PCI Express Slot on the carrier board.
3. The table represents a case when a single function PCI/PCIe device is connected to all possible slots on the carrier board. The given bus
numbers will change based on actual hardware configuration.