Congatec 045950 Скачать руководство пользователя страница 55

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2017

congatec

TSKLm16

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Signal

Pin # Description

I/O

PU/PD Comment

HDMI3_CTRLDATA

C37

TMDS I

C Control Data

Multiplexed with DDI3_CTRLDATA_AUX-

I/O OD 3.3V PU 100k

3.3V

HDMI3_CTRLDATA is a boot strap signal (see note below).
HDMI enable strap is already populated

Note

1. Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For

more information refer to section 9.2 “Boot Strap Signals”.

2. The conga-TS175 does not natively support TMDS. A DP++ to TMDS converter (e.g PTN3360D) needs to be implemented.

Table 17 DisplayPort (DP) Signal Descriptions

Signal

Pin # Description

I/O

PU/PD Comment

DP
DP1_LANE3-

D36
D37

Uni-directional main link for the transport of isochronous streams and secondary data.
Multiplexed with DDI and DDI1_PAIR3-.

O PCIE

DP
DP1_LANE2-

D32
D33

Uni-directional main link for the transport of isochronous streams and secondary data.
Multiplexed with DDI and DDI1_PAIR2-.

O PCIE

DP
DP1_LANE1-

D29
D30

Uni-directional main link for the transport of isochronous streams and secondary data.
Multiplexed with DDI and DDI1_PAIR1-.

O PCIE

DP
DP1_LANE0-

D26
D27

Uni-directional main link for the transport of isochronous streams and secondary data.
Multiplexed with DDI and DDI1_PAIR0-.

O PCIE

DP1_HPD

C24

Detection of Hot Plug / Unplug and notification of the link layer.
Multiplexed with DDI1_HPD.

I 3.3V

PD 1M

D15

Half-duplex bi-directional AUX channel for services such as link configuration or
maintenance and EDID access.

I/O PCIE PD 100k

DP1_AUX-

D16

Half-duplex bi-directional AUX channel for services such as link configuration or
maintenance and EDID access.

I/O PCIE PU 100k

3.3V

Boot strap signal (see note below)
Enable strap is already populated.

DP
DP2_LANE3-

D49
D50

Uni-directional main link for the transport of isochronous streams and secondary data.
Multiplexed with DDI and DDI2_PAIR3-

O PCIE

DP
DP2_LANE2-

D46
D47

Uni-directional main link for the transport of isochronous streams and secondary data.
Multiplexed with DDI and DDI2_PAIR2-

O PCIE

DP
DP2_LANE1-

D42
D43

Uni-directional main link for the transport of isochronous streams and secondary data.
Multiplexed with DDI and DDI2_PAIR1-

O PCIE

DP
DP2_LANE0-

D39
D40

Uni-directional main link for the transport of isochronous streams and secondary data.
Multiplexed with DDI and DDI1_PAIR0-

O PCIE

DP2_HPD

D44

Detection of Hot Plug / Unplug and notification of the link layer.
Multiplexed with DDI2_HPD.

I 3.3V

PD 1M

C32

Half-duplex bi-directional AUX channel for services such as link configuration or
maintenance and EDID access.

I/O PCIE PD 100k

Содержание 045950

Страница 1: ...COM Express conga TS175 7th Generation Intel Core i7 i5 i3 and Xeon processor with either QM175 HM175 or CM238 Chipset User s Guide Revision 1 6...

Страница 2: ...nsions Updated sections 4 1 CSA Dimensions 4 2 CSP Dimensions 4 3 HSP Dimensions Updated sections 11 3 Updating the BIOS and 11 4 Supported Flash Devices 1 5 2020 05 08 AEM Updated section 4 Cooling S...

Страница 3: ...any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing congatec AG a...

Страница 4: ...nless the device is contained within its original packaging Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty Symbols The following symbols are used in t...

Страница 5: ...non conformance to the agreed upon specifications will be repaired or exchanged at congatec s option and expense Customer will obtain a Return Material Authorization RMA number from congatec AG prior...

Страница 6: ...lities and drivers which have been made available to assist you If you still require assistance after visiting our website then contact our technical support department by email at support congatec co...

Страница 7: ...eDP 29 6 1 3 3 VGA 29 6 1 4 SATA 29 6 1 5 USB 30 6 1 6 Gigabit Ethernet 30 6 1 7 High Definition Audio HDA Interface 30 6 1 8 LPC Bus 30 6 1 9 I C Bus 31 6 1 10 ExpressCard 31 6 1 11 General Purpose...

Страница 8: ...out Tables 44 9 1 Connector Signal Descriptions 45 9 2 Boot Strap Signals 66 10 System Resources 67 10 1 I O Address Assignment 67 10 1 1 LPC Bus 67 10 2 PCI Configuration Space Map 68 10 3 I2 C 69 10...

Страница 9: ...Table 18 Embedded DisplayPort Signal Descriptions 56 Table 19 CRT Signal Descriptions 57 Table 20 LVDS Signal Descriptions 57 Table 21 Serial ATA Signal Descriptions 58 Table 22 USB 2 0 Signal Descri...

Страница 10: ...ype 6 pinout definition and comply with COM Express 2 1 specification They are equipped with two high performance connectors that ensure stable data throughput The COM computer on module integrates al...

Страница 11: ...Intel HM175 Intel Smart Cache 8 MB 6 MB 6 MB 3 MB 3 MB Processor Graphics Intel HD Graphics 630 GT2 Intel HD Graphics 630 GT2 Intel HD Graphics 630 GT2 Intel HD Graphics 630 GT2 Intel HD Graphics 630...

Страница 12: ...o Technology HD hardware accelerated video decode encode processing transcode Switchable Hybrid graphics Up to 3 independent displays 3x DP DP HDMI DVI 1x LVDS 1x VGA 1x PEG x16 port Gen 3 Resolutions...

Страница 13: ...by default because we recommend to operate the system in native UEFI mode 2 3 Mechanical Dimensions 125 0 mm x 95 0 mm Height approximately 18 or 21 mm including heatspreader depending on the carrier...

Страница 14: ...Input Range Volts Derated Input Volts Max Input Ripple 10Hz to 20MHz mV Max Module Input Power w derated input Watts Assumed Conversion Efficiency Max Load Power Watts VCC_12V 12 12 11 4 12 6 11 4 10...

Страница 15: ...Minimum value Lowest frequency mode LFM with minimum core voltage during desktop idle S0 Maximum value Highest frequency mode HFM Turbo Boost The CPU was stressed to its maximum frequency S0 Peak curr...

Страница 16: ...1 N A 0 61 2 36 2 79 0 09 0 06 045955 4 GB B 0 R004 Windows 10 Intel Xeon E3 1505MV6 4 3 0 4 0 0 61 5 56 6 28 0 09 0 06 045956 4 GB B 0 R004 Windows 10 Intel Xeon E3 1505LV6 4 2 2 3 0 0 62 3 15 3 49 0...

Страница 17: ...80 C Humidity Operation 10 to 90 Storage 5 to 95 Caution The above operating temperatures must be strictly adhered to at all times When using a congatec heatspreader the maximum operating temperature...

Страница 18: ...face TMDS Mobile Intel 100 Series PCH H MGMNT PECI PCIe Gen 3 Aux Channel 1 PCIe Gen 3 PECI SM Bus Dual Channel DDR4 eDP PCIe Gen 3 eDP to LVDS Bridge 2x SO DIMM X1 X2 SPI Flash 0 LVDS eDP TPM XDP LPC...

Страница 19: ...on the environmental conditions it is subjected to For more information about this subject contact your local congatec sales representative and request the gap pad material manufacturer s specificatio...

Страница 20: ...0 71 4 1 CSA Dimensions 7 3 0 2 F 28 F 7 3 M2 5 x 13 mm threaded standoff for threaded version or 2 7 x 13 mm non threaded standoff for borehole version 87 29 95 96 6 21 20 31 14 5 125 58 5 76 79 117...

Страница 21: ...AG TSKLm16 21 71 4 2 CSP Dimensions 87 14 5 31 117 76 58 5 79 M2 5 x 13 mm threaded standoff for threaded version or 2 7 x 13 mm non threaded standoff for borehole version 20 28 95 125 28 15 E E 0 62...

Страница 22: ...right 2017 congatec AG TSKLm16 22 71 4 3 HSP Dimensions M2 5 x 11 mm threaded standoff for threaded version or 2 7 x 11 mm non threaded standoff for borehole version 87 11 95 4 56 41 5 58 5 76 79 117...

Страница 23: ...They are often referred to as the superconductors of heat as they possess an extra ordinary heat transfer capacity and rate with almost no heat loss The thermal image below provides a reference to wh...

Страница 24: ...ensor The CPU temperature sensor T00 is located in the CPU U1 This sensor measures the CPU temperature and is defined in CGOS API as CGOS_TEMP_CPU The board temperature sensor T01 is located in the co...

Страница 25: ...of the module This sensor measures the temperature of the DRAM module and is defined in CGOS API as CGOS_TEMP_BOTDIMM_ENV The DRAM sensor location is shown below Note The optional DRAM sensors are not...

Страница 26: ...TS175 offers six PCI Express lanes on the A B connector and two lanes on the C D connector The lanes support up to 8 GT s Gen 3 speed a 8 x1 link configuration other link configurations requires a sp...

Страница 27: ...s The conga TS175 supports the following up to three DP DP HDMI DVI single or dual channel LVDS VGA three independent displays Table 8 shows the supported display combinations and resolutions PEG LANE...

Страница 28: ...304 60Hz 24 bpp 4096x2160 30Hz 24 bpp VGA 1920x1200 60Hz Option 4 DP or TMDS 4096x2304 60Hz 24 bpp 4096x2160 30Hz 24 bpp VGA 1920x1200 60Hz LVDS or eDP BOM Option 1920x1200 60Hz dual LVDS mode 4096x23...

Страница 29: ...ESA EDIDTM 1 3 resolution up to 1920x1200 in dual LVDS bus mode Note The LVDS eDP interface supports either LVDS or eDP signals Both interfaces are not supported simultaneously 6 1 3 3 VGA The conga T...

Страница 30: ...Intel i219 LM Phy The interface supports full duplex operation at 10 100 1000 Mb s and half duplex operation at 10 100 Mb s Note 1 The GBE0_LINK output is not active during a 10 Mb connection It is o...

Страница 31: ...UART interfaces are routed to the A B connector They do not support hardware handshake and flow control The UART interfaces require congatec device driver to function 6 1 12 GPIOs The conga TS175 off...

Страница 33: ...transistor stage the voltage measured at the PWR_OK input pin may be only around 0 8V when the 12V is applied to the module Actively driving PWR_OK high is compliant to the COM Express specification b...

Страница 34: ...in BIOS settings or by system software Standard 12V Power Supply Implementation Guidelines 12 volt input power is the sole operational power source for the conga TS175 The remaining necessary voltages...

Страница 35: ...The Deep Sx is a lower power state employed to minimize the power consumption while in S3 S4 S5 In the Deep Sx state the system entry condition determines if the system context is maintained or not A...

Страница 36: ...features 7 1 1 Board Information The cBC provides a rich data set of manufacturing and board information such as serial number EAN number hardware and firmware revisions and so on It also keeps track...

Страница 37: ...the correct speed readout 2 For the correct fan control FAN_PWMOUT FAN_TACHIN implementation see the COM Express Design Guide 7 2 OEM BIOS Customization The conga TS175 is equipped with congatec Embe...

Страница 38: ...ity CGUTIL 1 5 4 or later to replace add the OEM POST logo 7 2 4 OEM BIOS Code Data With the congatec embedded BIOS it is possible for system designers to add their own code to the BIOS POST process T...

Страница 39: ...and view the following documents congatec Battery Management Interface Specification Battery System Design Guide conga SBM3 User s Guide 7 4 API Support CGOS In order to benefit from the above mention...

Страница 40: ...ulating start stop the processor s internal clocks at a duty cycle of 25 on and 75 off When activated the TCC causes both processor core and graphics core to reduce frequency and voltage adaptively Th...

Страница 41: ...nd regular intervals until the upper limit is met or the maximum possible upside for the number of active cores is reached For more information about Intel Turbo Boost 2 Technology visit the Intel web...

Страница 42: ...to establish the appropriate trip points 8 1 5 Processor Performance Control Intel processors found on the conga TS175 run at different voltage frequency states performance states which is referred t...

Страница 43: ...e must be powered by standby power source Set USB Device Wakeup from S3 S4 to ENABLED in the ACPI setup menu if setup node is available in BIOS setup program In Device Manager look for the keyboard mo...

Страница 44: ...ted by the chip vendors only pull ups or pull downs implemented by congatec are listed For information about the internal pull ups or pull downs implemented by the chip vendors refer to the respective...

Страница 45: ...B0 A17 SATA0_TX B17 SATA1_TX A72 eDP_TX2 LVDS_A0 B72 LVDS_B0 A18 SUS_S4 B18 SUS_STAT A73 eDP_TX1 LVDS_A1 B73 LVDS_B1 A19 SATA0_RX B19 SATA1_RX A74 eDP_TX1 LVDS_A1 B74 LVDS_B1 A20 SATA0_RX B20 SATA1_RX...

Страница 46: ...A45 USB0 B45 USB1 A100 GND FIXED B100 GND FIXED A46 USB0 B46 USB1 A101 SER1_TX B101 FAN_PWMOUT A47 VCC_RTC B47 EXCD1_PERST A102 SER1_RX B102 FAN_TACHIN A48 EXCD0_PERST B48 EXCD1_CPPE A103 LID B103 SLE...

Страница 47: ...RSVD C72 PEG_RX6 D72 PEG_TX6 C18 RSVD D18 RSVD C73 GND D73 GND C19 PCIE_RX6 D19 PCIE_TX6 C74 PEG_RX7 D74 PEG_TX7 C20 PCIE_RX6 D20 PCIE_TX6 C75 PEG_RX7 D75 PEG_TX7 C21 GND FIXED D21 GND FIXED C76 GND D...

Страница 48: ...D100 GND FIXED C46 DDI3_PAIR2 D46 DDI2_PAIR2 C101 PEG_RX15 D101 PEG_TX15 C47 DDI3_PAIR2 D47 DDI2_PAIR2 C102 PEG_RX15 D102 PEG_TX15 C48 RSVD D48 RSVD C103 GND D103 GND C49 DDI3_PAIR3 D49 DDI2_PAIR3 C1...

Страница 49: ...ress Base Specification Revision 3 0 PCIE_RX4 PCIE_RX4 B55 B56 PCI Express channel 4 Receive Input differential pair I PCIE Supports PCI Express Base Specification Revision 3 0 PCIE_TX4 PCIE_TX4 A55 A...

Страница 50: ...X7 PEG_RX7 PEG_RX8 PEG_RX8 PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69 C...

Страница 51: ...D78 D79 D81 D82 D85 D86 D88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI Express Graphics Transmit Output differential pairs Note Can also be used as PCI Express Transmit Output differential pairs 16 thr...

Страница 52: ...ect HDMI DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V PU 100k 3 3V Boot strap signal see note below Enable strap is already populated DDI1_DDC_AUX_SEL D34 Selects the funct...

Страница 53: ...d HDMI3_HPD I 3 3V PD 1M DDI3_CTRLCLK_AUX C36 Multiplexed with DP3_AUX and HDMI3_CTRLCLK DP AUX function if DDI3_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high I O P...

Страница 54: ...7 TMDS differential pair Multiplexed with DDI2_PAIR2 and DDI2_PAIR2 O PCIE TMDS2_DATA1 TMDS2_DATA1 D42 D43 TMDS differential pair Multiplexed with DDI2_PAIR1 and DDI2_PAIR1 O PCIE TMDS2_DATA2 TMDS2_DA...

Страница 55: ...eams and secondary data Multiplexed with DDI1_PAIR0 and DDI1_PAIR0 O PCIE DP1_HPD C24 Detection of Hot Plug Unplug and notification of the link layer Multiplexed with DDI1_HPD I 3 3V PD 1M DP1_AUX D15...

Страница 56: ...ug Unplug and notification of the link layer Multiplexed with DDI3_HPD I 3 3V PD 1M DP3_AUX C36 Half duplex bi directional AUX channel for services such as link configuration or maintenance and EDID a...

Страница 57: ...DC data line I O OD 5V PU 1k2 3 3V Optional Table 20 LVDS Signal Descriptions Signal Pin Description I O PU PD Comment LVDS_A0 LVDS_A0 LVDS_A1 LVDS_A1 LVDS_A2 LVDS_A2 LVDS_A3 LVDS_A3 A71 A72 A73 A74 A...

Страница 58: ...dicator active low I O 3 3v Table 22 USB 2 0 Signal Descriptions Signal Pin Description I O PU PD Comment USB0 A46 USB Port 0 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB0 A45 U...

Страница 59: ...ll up for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3VSB PU 10k 3 3VSB Do not pull this line high on the...

Страница 60: ...e case in which the reference is shorted to ground the current shall be limited to 250mA or less Not connected Note 1 The GBE0_LINK output is not active during a 10 Mb connection It is only active dur...

Страница 61: ...k 3 3VSB EXCD0_PERST EXCD1_PERST A48 B47 ExpressCard Reset O 3 3V PU 10k 3 3V Table 27 LPC Signal Descriptions Signal Pin Description I O PU PD Comment LPC_AD 0 3 B4 B7 LPC multiplexed address command...

Страница 62: ...N_PWMOUT B101 Fan speed control Uses the Pulse Width Modulation PWM technique to control the fan s RPM O OD 3 3V FAN_TACHIN B102 Fan tachometer input I OD PU 10K 3 3V Requires a fan with a two pulse o...

Страница 63: ...may result from a low SYS_RESET input a low PWR_OK input a VCC_12V power input that falls below the minimum specification a watchdog timeout or may be initiated by the module software O 3 3V PD 100k...

Страница 64: ...port receiver I 3 3V PU 47k 3 3V SER1_RX A102 General purpose serial port receiver I 3 3V PU 47k 3 3V Table 33 Module Type Definition Signal Description Signal Pin Description I O Comment TYPE0 TYPE1...

Страница 65: ...iptions Signal Pin Description I O PU PD Comment VCC_12V A104 A109 B104 B109 C104 C109 D104 D109 Primary power input 12V nominal All available VCC_12V pins on the connector s shall be used P VCC_5V_SB...

Страница 66: ...X DP2_AUX HDM2_CTRLDATA C33 Multiplexed with DP2_AUX and HDMI2_CTRLDATA DP AUX function if DDI2_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V...

Страница 67: ...O cycles that are not positively decoded are forwarded to the PCI Bus not the LPC Bus Only specified I O ranges are forwarded to the LPC Bus In the congatec Embedded BIOS the following I O address ra...

Страница 68: ...e1 16h 02h ME IDE Redirection IDE R Interface 00h Note1 16h 03h ME Keyboard and Text KT Redirection 00h Note1 16h 04h Intel ME Interface 3 00h 17h 00h SATA Controller 00h 1Ch 00h Not connected PCI Exp...

Страница 69: ...visible only if a device is attached to the PCI Express Slot on the carrier board 3 The table represents a case when a single function PCI PCIe device is connected to all possible slots on the carrier...

Страница 70: ...ot have access to the restricted area of the congatec website contact your local congatec sales representative 11 1 Navigating the BIOS Setup Menu The BIOS setup menu shows the features and options su...

Страница 71: ...is not officially supported by congatec and therefore not recommended for critical tasks such as firmware updates We recommend to use only the UEFI shell for critical updates 11 4 Recovering from Ext...

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