Concurrent Technologies VP 110/01 Series, Техническое справочное руководство

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8.8 Long Duration Timer/Periodic Interrupt Timer
The Long Duration Timer (LDT) consists of a 32-bit free running counter with a 32-bit holding
register and a Status & Control register. The counter bytes are laid out in little-endian format to
permit multi-byte read/write operations. The Status & Control register controls the operation of
the LDT.
A 32-bit holding register is provided to ensure stable count values are read. Read operations
return the holding register byte values. A read operation on the low byte of the counter causes
the count value to be transferred to the holding register. Hence, the low byte should be read first
to ensure a stable count value.
The counter may be preset by writing to the registers. The counter bytes may be written
independently. The counter should be stopped before writing to it or the outcome may be
indeterminate. The counter registers are cleared at power-on, but not by subsequent reset
operations. If necessary, the LDT can be cleared by writing zero to all four counter bytes.
The LDT clock frequency is selectable from 2 sources: 1) SIO HF clock and 2) SIO LF clock.
The SIO (PC87417) HF clock frequency is selectable from an internally generated 48MHz clock
via a programmable divider. It is further divided by 4 in the LDT before being used. The LF
clock is derived from the 32kHz RTC clock. The following clock frequencies are available:-
HF Clock/4: 12, 6, 4, 3, 2, 1.5, 1, 0.75MHz
LF Clock: 32.768kHz
NOTE 1 1MHz is selected by the BIOS as the default clock frequency (SIO set to 4MHz) as
this is the clock frequency used on other Concurrent Technologies boards.
NOTE 2 Although the LFCLK can be configured to 1Hz it also drives other circuitry. It is
recommended that the LFCLK be left at 32.768kHz for future compatibility.
The clock mark/space ratio can be any value that meets the minimum high /low pulse widths of
40ns.
An interrupt may be generated when the counter rolls over (from FFFFFFFFh to zero). This
occurs approximately every 72 minutes (1MHz clock).
The LDT doubles as a simple Periodic Interrupt Timer (PIT). It offers 7 fixed interrupt rates,
namely: 100, 200, 500, 1,000, 2,000, 5,000 and 10,000Hz (1MHz clock). The mode/ interrupt
rate is set by three bits in the LDT Status & Control register. Scale the rates accordingly
depending on the chosen clock frequency with respect to a clock of 1MHz e.g. for a 2MHz clock
the interrupt rates will be: 200, 400, 1,000, 2,000, 4,000, 10,000 and 20,000Hz.
In PIT mode, the counter counts up to a pre-determined maximum value and then goes back to
zero. To ensure a full first interval, the low and mid-low bytes of the counter should be cleared
before the counter is started.
The LDT interrupt is always enabled when the timer is running. If this is not convenient, the
interrupt can be masked externally in the South Bridge PIC. The LDT/PIT interrupt service
routine must clear the interrupt flag using a read/modify/write sequence of accesses to the LDT
Status & Control register.
8-14 VP 110/01x
Additional Local I/O Functions