RAID Array 3000 Controller
2-7
Compaq Confidential – Need to Know Required
Writer: Bob Young Project: RAID Array 3000 Controller Shelf Hardware User’s Guide Comments:
Part Number: EK-SMCPQ-UG. D01 File Name: c-ch2 RAID Array 3000 Controller.doc Last Saved On: 12/4/00 1:08 PM
■
Any drive may be designated as a spare. Spares are global, meaning that
in the event of a drive failure, the controller will search for the first
available spare on any channel or SCSI ID and automatically begin
rebuilding the failed drive’s data.
■
All configuration and monitoring of RAID sets are accomplished via
SWCC with software platform kit.
The controller employs a number of techniques to achieve as much
performance as possible from its design.
Custom Components
To increase performance and reliability, the controller’s core functions have
been encapsulated in four custom Application Specific Integrated Circuits
(ASIC) components as follows:
■
XOR ASIC: Used in the exclusive-or parity calculations employed by
RAID levels 4 and 5.
■
DMA ASIC: Controls the data path hardware for the various I/O ports.
■
CPU Interface ASIC: Supports the controller’s MIPS R3000 RISC
central processing unit.
■
Memory Controller ASIC: Controls the memory system and supports
data movement on the internal bus at a maximum burst rate of 80 Mb/s
and a maximum sustainable rate of 60 Mb/s.
Efficient Write and Read Algorithms
Standard RAID write operations that involve parity, such as those in RAID
levels 4 and 5, require multiple, time-consuming steps:
1.
Read data from the parity drive.
2.
Read existing data from the target data drives.
3.
Exclusive-or the old parity, old data, and new data to generate new
parity data.
4.
Write the new parity data to the parity drive.
5.
Write the new data to the target data drives.
The controller uses several techniques to streamline write operations and
significantly improve performance. All the techniques use the controller’s on-
board cache 60 ns SIMMs.