Compaq Professional 5100 Скачать руководство пользователя страница 12

T

ECHNOLOGY 

B

RIEF

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ECG066/1198

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AGPset Architecture

The 440LX AGPset (LX chipset) from Intel is designed primarily for the commercial desktop and
consumer desktop markets.  However, some workstation vendors are deploying the LX chipset in
machines targeted for workstation applications.  Key features of the LX architecture include

 

Single PCI bus

 

Single memory bus

 

66-MHz SDRAM memory

 

Advanced graphics port (AGP) bus for graphics cards

 

Support for up to two Intel Pentium II processors

Figure 9 illustrates the LX chipset architecture. The microprocessor, memory, and AGP graphics
buses operate with a peak bandwidth of 533 MB/s, while the peak bandwidth of the PCI bus is
133 MB/s.   This contrasts with the 1.07-GB/s peak memory bandwidth and the 267-MB/s PCI
bus bandwidth of the Highly Parallel System Architecture.

CPU

CPU

Memory

Controller

SCSI

Controller

Di
sk

PCI Slots and
other Devices

PCI

Controller

AGP

Controller

Graphics

Controller

A single PCI bus provides
133 MB/s bandwidth for
all attached I/O devices

A single memory
controller provides
maximum bandwidth of
533 MB/s.

The AGP bus provides a dedicated path
for the graphics controller to
communicate with main memory and
processors.  The AGP-to-memory bus
provides bandwidth of 533 MB/s.

Figure 9.  Block diagram of the LX architecture.

The Highly Parallel System Architecture supports industry-standard EDO memory arranged in
2:1 interleaved banks.  The LX architecture uses 66-MHz SDRAM technology, which Compaq
projects to be a very short-lived technology, based on imminent microprocessor and system
architecture advancements.  Specifically, Compaq expects that 100-MHz SDRAM will be
available as soon as 100-MHz host-bus systems are available—sometime in the first half of 1998.
Since dual-processor LX workstations are not expected to be generally available until sometime
during the fourth quarter 1997, the 66-MHz SDRAM for workstations may have a useful life of
only about four to six months.  Large purchases of 66-MHz SDRAM could result in large
obsolescence costs as early as next year, when users migrate to higher performance 100-MHz
SDRAM technology.  This can be a significant expense for customers, as most workstation
applications require large memory configurations.  The Highly Parallel System Architecture, on
the other hand, uses proven EDO memory technology that is supported by other Compaq
enterprise products.  Customers who plan to migrate to 100-MHz SDRAM next year will be able
to protect and fully amortize their investment in EDO memory by redeploying the EDO memory
into other systems, such as ProLiant servers and other workstations.

Содержание Professional 5100

Страница 1: ...tion DCC place growing demands on system resources increasing system bandwidth becomes a critical business issue After evaluating available system architectures Compaq determined that only a new highl...

Страница 2: ...TwinTray ROMPaq LicensePaq QVision SLT ProLinea SmartStart NetFlex DirectPlus QuickFind RemotePaq BackPaq TechPaq SpeedPaq QuickBack PaqFax Presario SilentCool CompaqCare design Aero SmartStation Min...

Страница 3: ...s from other architectures used in X86 systems ARCHITECTURE OVERVIEW Unlike any previous architecture used in X86 systems the new architecture being implemented by Compaq incorporates a highly paralle...

Страница 4: ...sional Workstation 8000 will use the 200 MHz Pentium Pro processor with an integrated 512 KB L2 cache that runs at the core processor speed of 200 MHz The high speed processor and cache provide top pe...

Страница 5: ...nd SMP aware applications Each memory bus is 144 bits wide and consists of 128 bits of data plus 16 bits for Error Checking and Correction ECC The new architecture uses buffered 60 ns Extended Data Ou...

Страница 6: ...arge CAS Precharge Figure 4 Basic timeline for sequential reads from the same page of DRAM While it is fairly common for a single processor to access consecutive memory locations consecutive cycles in...

Страница 7: ...MB 2 x 128 MB 4 512 MB 4 x 64 MB 4 x 64 MB 1 512 MB 6 x 64 MB 2 x 64 MB 2 512 MB 8 x 64 MB 3 512 MB 4 x 128 MB 4 1 GB 8 x 64 MB 4 x 128 MB 1 1 GB 4 x 128 MB 4 x 128 MB 2 1 GB 8 x 128 MB 3 1 GB 4 x 256...

Страница 8: ...bus It is controlled by an I O cache controller When a PCI bus master requests data from system memory the I O cache controller automatically reads a full cache line 32 bytes from system memory at the...

Страница 9: ...up to 1 07 GB s two to four times the bandwidth of other NT X86 systems Furthermore with dual peer PCI buses high bandwidth peripherals can be placed on separate PCI buses CPU CPU Memory Controller S...

Страница 10: ...hics controller to access separate memory pools concurrently Furthermore the ELSA Gloria L 3D graphics board and the Diamond Fire GL 4000 3D graphics board available with the new Compaq workstations h...

Страница 11: ...tively However a crossbar switch is an expensive solution in a system with several buses The reason is that all the buses must go into a single chip that has sufficient pins for each bus This requires...

Страница 12: ...o memory bus provides bandwidth of 533 MB s Figure 9 Block diagram of the LX architecture The Highly Parallel System Architecture supports industry standard EDO memory arranged in 2 1 interleaved bank...

Страница 13: ...eaks of up to 40 percent Thus PCI graphics cards still have headroom to double performance without saturating the PCI bus The dual PCI buses in the Highly Parallel System Architecture in some cases pr...

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