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T

ECHNOLOGY 

B

RIEF

 

1

ECG066/1198

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November 1998

Compaq Computer
Corporation

ISSD Technology
Communications

C

O N T E N T S

Introduction ......................3

Architecture Overview.......3

Advanced SMP ..................3

Pentium Pro Processor ........ 4

Pentium II Processor ........... 4

Dual Memory Buses ..........5

Dual-Peer PCI Buses .........8

Multiple Drives..................8

Alternative
Architectures ....................9

Typical NT/X86
Architecture ....................... 9

Unified Memory
Architecture ....................... 9

Crossbar Switch
Architecture ..................... 11

AGPset Architecture .......... 12

Conclusion ..................... 13

Highly Parallel System Architecture for
Compaq Professional Workstations
5100, 6000, and 8000

As critical applications for financial analysis, computer-aided design (CAD), computer-
aided engineering (CAE), and digital content creation (DCC) place growing demands on
system resources, increasing system bandwidth becomes a critical business issue.  After
evaluating available system architectures, Compaq determined that only a new, highly
parallel system architecture could provide the required levels of performance, processor
and I/O expandability, and bandwidth to satisfy the needs of workstation users.  Compaq
is therefore implementing a new architecture that delivers the greatest bandwidth
available today for systems running such demanding applications under the Microsoft
Windows NT operating system.

This technology brief describes the new Highly Parallel System Architecture and
differentiates it from other architectures used in X86 systems.

Please direct comments regarding this communication to the ISSD Technology Communications Group at this Internet address:

[email protected]

Содержание Professional 5100

Страница 1: ...tion DCC place growing demands on system resources increasing system bandwidth becomes a critical business issue After evaluating available system architectures Compaq determined that only a new highl...

Страница 2: ...TwinTray ROMPaq LicensePaq QVision SLT ProLinea SmartStart NetFlex DirectPlus QuickFind RemotePaq BackPaq TechPaq SpeedPaq QuickBack PaqFax Presario SilentCool CompaqCare design Aero SmartStation Min...

Страница 3: ...s from other architectures used in X86 systems ARCHITECTURE OVERVIEW Unlike any previous architecture used in X86 systems the new architecture being implemented by Compaq incorporates a highly paralle...

Страница 4: ...sional Workstation 8000 will use the 200 MHz Pentium Pro processor with an integrated 512 KB L2 cache that runs at the core processor speed of 200 MHz The high speed processor and cache provide top pe...

Страница 5: ...nd SMP aware applications Each memory bus is 144 bits wide and consists of 128 bits of data plus 16 bits for Error Checking and Correction ECC The new architecture uses buffered 60 ns Extended Data Ou...

Страница 6: ...arge CAS Precharge Figure 4 Basic timeline for sequential reads from the same page of DRAM While it is fairly common for a single processor to access consecutive memory locations consecutive cycles in...

Страница 7: ...MB 2 x 128 MB 4 512 MB 4 x 64 MB 4 x 64 MB 1 512 MB 6 x 64 MB 2 x 64 MB 2 512 MB 8 x 64 MB 3 512 MB 4 x 128 MB 4 1 GB 8 x 64 MB 4 x 128 MB 1 1 GB 4 x 128 MB 4 x 128 MB 2 1 GB 8 x 128 MB 3 1 GB 4 x 256...

Страница 8: ...bus It is controlled by an I O cache controller When a PCI bus master requests data from system memory the I O cache controller automatically reads a full cache line 32 bytes from system memory at the...

Страница 9: ...up to 1 07 GB s two to four times the bandwidth of other NT X86 systems Furthermore with dual peer PCI buses high bandwidth peripherals can be placed on separate PCI buses CPU CPU Memory Controller S...

Страница 10: ...hics controller to access separate memory pools concurrently Furthermore the ELSA Gloria L 3D graphics board and the Diamond Fire GL 4000 3D graphics board available with the new Compaq workstations h...

Страница 11: ...tively However a crossbar switch is an expensive solution in a system with several buses The reason is that all the buses must go into a single chip that has sufficient pins for each bus This requires...

Страница 12: ...o memory bus provides bandwidth of 533 MB s Figure 9 Block diagram of the LX architecture The Highly Parallel System Architecture supports industry standard EDO memory arranged in 2 1 interleaved bank...

Страница 13: ...eaks of up to 40 percent Thus PCI graphics cards still have headroom to double performance without saturating the PCI bus The dual PCI buses in the Highly Parallel System Architecture in some cases pr...

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