A
A
B
B
C
C
D
D
E
E
1
1
2
2
3
3
4
4
NB_RESET#
NB_REFCLK_N
GMCH_CRT_VSYNC
GMCH_CRT_HSYNC
NB_ALLOW_LDTSTOP
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
+VDDLTP18
+VDDLT18
+VDDLT18
+AVDDDI
+NB_HTPVDD
DAC_RSET
+NB_PLLVDD
GMCH_LCD_CLK
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_LCD_DATA
POWER_SEL
+VDDLTP18
+AVDDQ
NB_PWRGD_R
+
AVDD1
NB_PWRGD_R
VARY_ENBKL
GMCH_ENBKL
CLK_NB_14.318M
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_R
GMCH_CRT_CLK
GMCH_CRT_DATA
GMCH_CRT_CLK
GMCH_CRT_DATA
NB_PWRGD
GMCH_ENBKL
VGA_ENBKL
AUX0N
NB_LDTSTOP#
CLK_NBGFX
CLK_NBGFX#
NB_REFCLK_P
NB_PWRGD
<27>
CLK_NBGFX
<22>
CLK_NBGFX#
<22>
CLK_SBLINK_BCLK
<22>
CLK_SBLINK_BCLK#
<22>
CLK_NBHT
<22>
CLK_NBHT#
<22>
A_RST#
<14,26,36>
SUS_STAT# <27>
SUS_STAT_R# <14>
ALLOW_LDTSTOP
<26>
POWER_SEL
<48>
SB_PWRGD
<8,27,36>
GMCH_LCD_DATA
<23,38>
GMCH_LCD_CLK
<23>
GMCH_ENVDD <23>
GMCH_INVT_PWM <23>
GMCH_CRT_R
<25>
GMCH_CRT_G
<25>
GMCH_CRT_B
<25>
GMCH_CRT_HSYNC
<14,25>
GMCH_CRT_VSYNC
<14,25>
GMCH <23>
GMCH_TXOUT0- <23>
GMCH <23>
GMCH_TXOUT1- <23>
GMCH <23>
GMCH_TXOUT2- <23>
GMC <23>
GMCH_TXCLK- <23>
GMCH_CRT_DATA
<25>
GMCH_CRT_CLK
<25>
AUX0N
<38>
VGA_ENBKL
<16>
ENBKL
<36>
LDT_STOP#
<8,26>
NB_DISP_CLKP
<26>
NB_DISP_CLKN
<26>
CLK_NB_14.318M
<22>
+1.8VS
+1.8VS
+VDDA18HTPLL
+VDDA18PCIEPLL
+1.1VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+3VS
+1.8VS
+1.8VS
+NB_PLLVDD
+NB_HTPVDD
+VDDA18PCIEPLL
+VDDA18HTPLL
+NB_HTPVDD
+1.8VS
+1.1VS
+3VS
+NB_PLLVDD
+1.8VS
+3VS
+3VS
+1.8VS
+1.8VS
+1.8VS
Title
Size
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
13
55
Tuesday, September 14, 2010
2008/10/06
2010/03/12
Compal Electronics, Inc.
Title
Size
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
13
55
Tuesday, September 14, 2010
2008/10/06
2010/03/12
Compal Electronics, Inc.
Title
Size
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
13
55
Tuesday, September 14, 2010
2008/10/06
2010/03/12
Compal Electronics, Inc.
Strap pin
POWER_SEL
HIGH
0.95V
1.1V
LOW
RS880
To SB
EMI
125m
A
20mA
4mA
65mA
20mA
20mA
120mA
15mA
300mA
RS880 A11(SA000032710)
If support VB, pop VB@ and reserve R71
PD on chip side
Wire-OR
AMD suggest
Check if needed?
R80
4.7K_0402_5%
R80
4.7K_0402_5%
1
2
C150
2.2U_0603_6.3V4Z
C150
2.2U_0603_6.3V4Z
1
2
C684
0.1U_0402_16V4Z
C684
0.1U_0402_16V4Z
1
2
PART 3 OF 6
PM
CL
O
CKs
PLL PWR
MIS.
CRT/TVOUT
LVTM
U3C
RS780M_FCBGA528
PART 3 OF 6
PM
CL
O
CKs
PLL PWR
MIS.
CRT/TVOUT
LVTM
U3C
RS780M_FCBGA528
VDDA18HTPLL
H17
SYSRESETb
D8
POWERGOOD
A10
LDTSTOPb
C10
ALLOW_LDTSTOP
C12
REFCLK_P/OSCIN(OSCIN)
E11
PLLVDD(NC)
A12
HPD(NC)
D10
DDC_CLK0/AUX0P(NC)
A8
DDC_DATA0/AUX0N(NC)
B8
THERMALDIODE_P
AE8
THERMALDIODE_N
AD8
I2C_CLK
B9
STRP_DATA
B10
GFX_REFCLKP
T2
GFX_REFCLKN
T1
GPP_REFCLKP
U1
GPP_REFCLKN
U2
PLLVDD18(NC)
D14
PLLVSS(NC)
B12
TXOUT_L0P(NC)
A22
TXOUT_L0N(NC)
B22
TXOUT_L1P(NC)
A21
TXOUT_L1N(NC)
B21
TXOUT_L2P(NC)
B20
TXOUT_L2N(DBG_GPIO0)
A20
TXOUT_L3P(NC)
A19
TXOUT_U0P(NC)
B18
TXOUT_L3N(DBG_GPIO2)
B19
TXOUT_U0N(NC)
A18
TXOUT_U1P(PCIE_RESET_GPIO3)
A17
TXOUT_U1N(PCIE_RESET_GPIO2)
B17
TXOUT_U2P(NC)
D20
TXOUT_U2N(NC)
D21
TXOUT_U3P(PCIE_RESET_GPIO5)
D18
TXOUT_U3N(NC)
D19
TXCLK_LP(DBG_GPIO1)
B16
TXCLK_LN(DBG_GPIO3)
A16
TXCLK_UP(PCIE_RESET_GPIO4)
D16
TXCLK_UN(PCIE_RESET_GPIO1)
D17
VDDLTP18(NC)
A13
VSSLTP18(NC)
B13
C_Pr(DFT_GPIO5)
E17
Y(DFT_GPIO2)
F17
COMP_Pb(DFT_GPIO4)
F15
RED(DFT_GPIO0)
G18
TMDS_HPD(NC)
D9
I2C_DATA
A9
TESTMODE
D13
HT_REFCLKN
C24
HT_REFCLKP
C25
SUS_STAT#(PWM_GPIO5)
D12
GREEN(DFT_GPIO1)
E18
BLUE(DFT_GPIO3)
E19
DAC_VSYNC(PWM_GPIO6)
B11
DAC_HSYNC(PWM_GPIO4)
A11
DAC_RSET(PWM_GPIO1)
G14
AVDD1(NC)
F12
AVDD2(NC)
E12
REDb(NC)
G17
GREENb(NC)
F18
AVDDDI(NC)
F14
AVSSDI(NC)
G15
AVDDQ(NC)
H15
AVSSQ(NC)
H14
VDDLT18_2(NC)
B15
VDDLT33_1(NC)
A14
VDDLT33_2(NC)
B14
VSSLT1(VSS)
C14
VSSLT2(VSS)
D15
VDDLT18_1(NC)
A15
VSSLT3(VSS)
C16
VSSLT4(VSS)
C18
VSSLT5(VSS)
C20
LVDS_DIGON(PCE_TCALRP)
E9
LVDS_BLON(PCE_RCALRP)
F7
LVDS_ENA_BL(PWM_GPIO2)
G12
VSSLT6(VSS)
E20
VDDA18PCIEPLL1
D7
VDDA18PCIEPLL2
E7
BLUEb(NC)
F19
AUX_CAL(NC)
C8
GPPSB_REFCLKP(SB_REFCLKP)
V4
GPPSB_REFCLKN(SB_REFCLKN)
V3
DDC_DATA1/AUX1N(NC)
A7
DDC_CLK1/AUX1P(NC)
B7
DAC_SCL(PCE_RCALRN)
F8
DAC_SDA(PCE_TCALRN)
E8
REFCLK_N(PWM_GPIO3)
F11
VSSLT7(VSS)
C22
RSVD
G11
R64
0_0402_5%
@
R64
0_0402_5%
@
1
2
L4
FBMA-L11-160808-221LMT 0603
L4
FBMA-L11-160808-221LMT 0603
1
2
L5
FBMA-L11-160808-221LMT 0603
L5
FBMA-L11-160808-221LMT 0603
1
2
C144
2.2U_0603_6.3V4Z
C144
2.2U_0603_6.3V4Z
1
2
C142
1U_0402_6.3V4Z
C142
1U_0402_6.3V4Z
1
2
R71
0_0402_5%
@
R71
0_0402_5%
@
1
2
C147
1U_0402_6.3V4Z
C147
1U_0402_6.3V4Z
1
2
R69
4.7K_0402_5%
EXT@
R69
4.7K_0402_5%
EXT@
1
2
U4
NC7SZ08P5X_NL_SC70-5
@
U4
NC7SZ08P5X_NL_SC70-5
@
B
2
A
1
Y
4
P
5
G
3
L2
FBMA-L11-160808-221LMT 0603
L2
FBMA-L11-160808-221LMT 0603
1
2
L6
FBMA-L11-160808-221LMT 0603
L6
FBMA-L11-160808-221LMT 0603
1
2
R456
0_0402_5%
INT@
R456
0_0402_5%
INT@
1
2
L7
FBMA-L11-160808-221LMT 0603
L7
FBMA-L11-160808-221LMT 0603
1
2
R90
1K_0402_5%
R90
1K_0402_5%
1
2
R85
150_0402_1%
R85
150_0402_1%
1
2
G
D
S
Q62
2N7002_SOT23
VGA@
G
D
S
Q62
2N7002_SOT23
VGA@
2
1
3
L3
FBMA-L11-160808-221LMT 0603
L3
FBMA-L11-160808-221LMT 0603
1
2
U8
NC7SZ08P5X_NL_SC70-5
U8
NC7SZ08P5X_NL_SC70-5
B
2
A
1
Y
4
P
5
G
3
L9
FBMA-L11-160808-221LMT 0603
L9
FBMA-L11-160808-221LMT 0603
1
2
C143
1U_0402_6.3V4Z
C143
1U_0402_6.3V4Z
1
2
C145
0.1U_0402_16V4Z
C145
0.1U_0402_16V4Z
1
2
R149
4.7K_0402_5%
R149
4.7K_0402_5%
1
2
R506
4.7K_0402_5%
INT@
R506
4.7K_0402_5%
INT@
1
2
C157
4.7U_0805_10V4Z
C157
4.7U_0805_10V4Z
1
2
R79
4.7K_0402_5%
R79
4.7K_0402_5%
1
2
R536
0_0402_5%
EXT@
R536
0_0402_5%
EXT@
1
2
R439
0_0402_5%
INT@
R439
0_0402_5%
INT@
1
2
R67
0_0402_5%
R67
0_0402_5%
1
2
C158
100P_0402_25V8K
@C158
100P_0402_25V8K
@
1
2
R73
4.7K
_0402_5%
R73
4.7K
_0402_5%
1
2
C151
1U_0402_6.3V4Z
C151
1U_0402_6.3V4Z
1
2
L10
BLM18AG601SN1D_2P
L10
BLM18AG601SN1D_2P
1
2
G
D
S
Q63
2N7002_SOT23
G
D
S
Q63
2N7002_SOT23
2
1
3
C146
2.2U_0603_6.3V4Z
C146
2.2U_0603_6.3V4Z
1
2
R89
150_0402_1%
R89
150_0402_1%
1
2
R66
0_0402_5%
R66
0_0402_5%
1
2
R75
4.7K
_0402_5%
R75
4.7K
_0402_5%
1
2
C149
1U_0402_6.3V4Z
C149
1U_0402_6.3V4Z
1
2
C154
2.2U_0603_6.3V4Z
C154
2.2U_0603_6.3V4Z
1
2
R72
0_0402_5%
VB@
R72
0_0402_5%
VB@
1
2
R82
2K_0402_5%
R82
2K_0402_5%
1
2
R86
100_0402_5%
@
R86
100_0402_5%
@
1
2
L8
FBMA-L11-160808-221LMT 0603
L8
FBMA-L11-160808-221LMT 0603
1
2
C148
2.2U_0603_6.3V4Z
C148
2.2U_0603_6.3V4Z
1
2
R78
4.7K_0402_5%
R78
4.7K_0402_5%
1
2
R81
0_0402_5%
R81
0_0402_5%
1
2
C155
1U_0402_6.3V4Z
C155
1U_0402_6.3V4Z
1
2
C152
1U_0402_6.3V4Z
C152
1U_0402_6.3V4Z
1
2
R63
2.2K_0402_5%
R63
2.2K_0402_5%
1
2
R70
4.7K_0402_5%
EXT@
R70
4.7K_0402_5%
EXT@
1
2
R84
1.8K_0402_5%
R84
1.8K_0402_5%
1
2
R504
4.7K_0402_5%
INT@
R504
4.7K_0402_5%
INT@
1
2
G
D
S
Q41
2N7002_SOT23
UMA@
G
D
S
Q41
2N7002_SOT23
UMA@
2
1
3
R65
715_0402_1%
R65
715_0402_1%
1
2
R88
150_0402_1%
R88
150_0402_1%
1
2
R68
300_0402_5%
R68
300_0402_5%
1
2
R417
300_0402_5%
@
R417
300_0402_5%
@
1
2
R77
4.7K_0402_5%
R77
4.7K_0402_5%
1
2
C141
2.2U_0603_6.3V4Z
C141
2.2U_0603_6.3V4Z
1
2
R173
4.7K_0402_5%
@
R173
4.7K_0402_5%
@
1
2
R74
4.7K
_0402_5%
R74
4.7K
_0402_5%
1
2
R76
0_0402_5%
VB@
R76
0_0402_5%
VB@
1
2
C156
0.1U_0402_16V4Z
C156
0.1U_0402_16V4Z
1
2
C679
22U_0805_6.3V6M
C679
22U_0805_6.3V6M
1
2
R91
0_0402_5%
R91
0_0402_5%
1
2
R106
4.7K_0402_5%
R106
4.7K_0402_5%
1
2
R87
140_0402_1%
R87
140_0402_1%
1
2
C153
2.2U_0603_6.3V4Z
C153
2.2U_0603_6.3V4Z
1
2
