Clevo M190S, Руководство по обслуживанию

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Schematic Diagrams
650-3 (LVDS Interface) - 3 of 4 (71-M1900-D02) B - 11
Schematic Diagrams
650-3 (LVDS Interface) - 3 of 4
Sheet 9 of 34
650-3
(LVDS Interface)
3 of 4
+3VS
+1.8VS
+1.8VS
+3VS
+3VS
+1.8VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
INTA# (12)
PCIRST#(12,13,18,19,20,22)
PWRGD(14,23)
REFCLK0 (4)
ZCLK0 (4)
ZUREQ (12)
ZDREQ (12)
AUXOK (14,22,29,30)
ROUT (10)
GOUT (10)
BOUT (10)
HSYNC (10)
VSYNC (10)
DDC1CLK(10)
DDC1DATA(10)
ZSTB0 (12)
ZSTB#0 (12)
ZSTB1 (12)
ZSTB#1 (12)
ZAD[0..15] (12)
VAD1 (5)
VAD6 (5)
VBCLK (5)
VBVSYNC (5)
VBD10 (5)
VBD3 (5)
CLKOUTP(10)
VBHSYNC (5)
Y0P (10)
CLKOUTM(10)
Y1P (10)
VAD9 (5)
VAD3 (5)
VBD7 (5)
VAD8 (5) Y2P (10)
VBD11 (5)
VBDE (5)
VBD5 (5)
VAD2 (5)
VBD4 (5)
VBD6 (5)
VBGCLK (5)
VAD0 (5)
VAD11 (5)
Y0M (10)
Y2M (10)
VAD7 (5)
VAD10 (5)
VBD2 (5)
Y1M (10)
REFCLK0
ROUT
GOUT
BOUT
Z0801 HSYNC
Z0802 VSYNC
DDC1CLK
DDC1DATA
INTA#
Z1XAVDD
CSYNC
RSYNC
LSYNC
RSYNC
PWRGD
AUXOK
ENTEST
ZAD10
ZSTB0
ZAD12
ZAD6
ZSTB#0
ZAD8
ZSTB#1
ZCMP_P
ZAD15
ZCLK0
ZAD14
ZAD9
ZAD1
ZAD0
ZUREQ
ZDREQ
ZAD7
ZVREF
ZAD2
ZAD13
ZAD11
ZAD5
ZAD3
ZSTB1
ZAD4
TRAP1
TRAP0
TMODE2
TMODE1
TMODE0
DLLEN-
ENTEST
ECLKAVSS
ECLKAVDD
DCLKAVDD
VVBWN
DACAVSS
VRSET
DACAVDD
VCOMP
Z1XAVSS
Z4XAVSS
Z4XAVDD
ZCMP_N
VDDZCMP
VSSZCMP
ZAD[0..15]
VAD8
VAD7
VBDE
VBD5
VBD2
VBD4
VBD10
Y0M
Y1P
VAD9
VAD2
Y0P
VAD11
CLKOUTM
Y2P
Y2M
VBD7
VBD3
VBD6
VBD11
VAD3
VAD10
CLKOUTP
VBGCLK
TXCLKIN
VAD6
VBHSYNC
Y1M
VBCLK
VBVSYNC
VAD0
VAD1
VBGCLK
TXCLKIN
C70
0.01UF
N12
L53
BK1608HS121
1 2
L56
BK1608HS121
1 2
L51
BK1608HS121
1 2
N10
L14
BK1608HS121
1 2
N7
C66 0.1UF
C67 0.1UF
C269
10UF/16V
C71
0.1UF
C61
0.01UF
C289
0.1UF
C306
0.1UF
C59
0.01UF
C365
10UF/16V
C349
0.1UF
C302
10UF/16V
C286
10UF/16V
C362
0.1UF
C361
0.01UF
C317
0.01UF
C318
0.1UF
R36
56
R267
150 1%
R275
150 1%
R254
33
R38
33
C336
0.1UF
C350
0.1UF
C352
1UF
C60
0.1UF
N1
C267
10UF/16V
C69
0.1UF
L12
BK1608HS121
1 2
R312
130_1%
R253 4.7K
R255 4.7K
T
T
T
U3C
SIS650
C15
A12
B13
A13
F13
E13
D13
D12
B11
E12
A11
F12
E14
D14
F14
B12
C12
C13
C14
B15
A15
B14
A14
F10
E11
C11
F11
A10
D11
E10
Y3
W4
W6
V2
V1
W1
W2
V5
U4
U2
V6
U3
T4
R3
T5
T6
R2
R6
R1
R4
P4
N3
P5
P6
N1
N6
N2
N4
P1
P3
T3
T1
U6
U1
V3
VOSCI
ROUT
GOUT
BOUT
HSYNC
VSYNC
VGPIO0
VGPIO1
INT#A
CSYNC
RSYNC
LSYNC
VCOMP
VRSET
VVBWN
DACAVDD1
DACAVSS1
DACAVDD2
DACAVSS2
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
ENTEST
DLLEN#
TESTMODE0
TESTMODE1
TESTMODE2
TRAP1
TRAP0
PCIRST#
PWROK
AUXOK
Z4XAVDD
Z4XAVSS
Z1XAVDD
Z1XAVSS
VDDZCMP
ZCMP_N
ZCMP_P
VSSZCMP
ZVREF
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZSTB1
ZSTB#1
ZSTB0
ZSTB#0
ZUREQ
ZDREQ
ZCLK
R39
56
C268
10UF/16V
L13
BK1608HS121
1 2
N2
L36 0(0805)
T
T
T
T
T
T
T
C39
1000P
C249
4.7U
R225 0
R218
4.7K
C43
1000P
C248
0.1UF
R217 10
R241
0
C237
4.7U
L39 0(0805)
R240 0(R)
C247
1000P
C239
0.1UF
RN11
8P4R-0
8 1
7 2
6 3
5 4
RN10
8P4R-0
8 1
7 2
6 3
5 4
U1
SN75LVDS84A
43
29
27 46
5
11
17
24
22
23
25
26
37
4
6
7
9
10
12
44
45
47
48
1
3
13
15
16
18
19
20
28
30
2
8
14
21
31
36
42
40
41
38
39
34
35
32
33
N/C
PLLVCC
PWRDWN# GND
GND
GND
GND
GND
TXIN18
TXIN19
TXIN20
TXCLKIN
LVDSVCC
TXIN6
TXIN7
TXIN8
TXIN9
TXIN10
TXIN11
TXIN0
TXIN1
TXIN2
TXIN3
TXIN4
TXIN5
TXIN12
TXIN13
TXIN14
TXIN15
TXIN16
TXIN17
PLLGND
PLLGND
VCC
VCC
VCC
VCC
LVDSGND
LVDSGND
LVDSGND
TXOUT0-
TXOUT1-
TXOUT2-
TXCLKO-
T
C42
1000P
RN9
8P4R-0
8 1
7 2
6 3
5 4
C238
1000P
C252
4.7U
C40
1000P
L34 0(0805)
R212 10
R545
R
R541
R
C652
0.1U(R)
R543 R
R542 R
U35
P2010(R)
1
6
2
3
8
7
5
4
XIN/CLK
MODout
XOUT
FS0
VDD
SR0
SSON
VSS
R226 0
RN1
8P4R-0
8 1
7 2
6 3
5 4
R540
R
R544 R
T
650-3
VGA
HyperZip
DLLEN#
DRAM_SEL
TRAP0
TRAP1
SDR
LSYNC
CSYNC
RSYNC
1(DDR)
(30~50K Ohm) Default
DDR
0
1
0
embedded pull-low
0
0 yes
disable PLL
yes
1
NB debug mode
0
yes
0
normal
NOTE: This page is for universal PCB design( suitable for both 645 or 650)
NB Hardware Trap Table
enable panel link
enable VGA interface
enable PLL
TV selection, NTSC/PAL(0/1)
enable VB
35.4mA
6.49mA
7.92mA
84.8mA
7.57mA
18.07mA
20MIL
10MIL
10MIL
10MIL
20MIL
10MIL