Clevo L295N, Руководство по обслуживанию

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Schematic Diagrams
B - 18 ICH7-M 4/4
B.Schematic Diagrams
ICH7-M 4/4
Sheet 17 of 38
ICH7-M 4/4
1.5VS_PCIE_ICH
L61 0_12
1.5VS_PCIE_ICH
Place within 100mils
of ICH on the bottom
side or 140 mils on
the top
3.3V
R317
10_06
C514
0.1U__16V_04
C522
0.1U__16V_04
C449
0.1U__16V_04
3.3VS
C506
0.1U__16V_04
C466
0.1U__16V_04
C532
0.1U__16V_04
Place on secondary
side under MCH
1.5VS
C444
1U_X5R_06
C507
0.1U__16V_04
1.5VS
C487
0.1U__16V_04
Layout note:
Layout note:
3.3VS
C525
0.1U__16V_04
5VS
C467
0.1U__16V_04
C505
1U_X5R_06
Layout note:
5VS
1.5VS_PCIE_ICH
Place within 100mils of ICH
on the bottom side or 140
mils on the top near pin
AG9
1.5VS
C229
0.1U__16V_04
D9
SCS751V-40
A
C
Place within 100 mils
of ICH7 on the bottom
side of 140mils on
the top
1.5VS
3.3V
C443
10U_10V_08
C484
0.1U__16V_04
C464
0.1U__16V_04
1.5VS_PCIE_ICH
C519
0.1U__16V_04
C523
0.1U__16V_04
VCC5REF
3.3V
CLOSE TO pin W5
3.3V
C531
0.1U__16V_04
3.3V
C472
1U_X5R_06
C166
0.01U_16V_04
C159
10U_10V_08
1.5VS
Layout note:
C548
0.1U__16V_04
V5REF_SUS
1.05VS
U8E
ICH7-M
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
+
C492
100U_6.3V_B
C481
0.1U__16V_04
Layout note:
1.5VS_PCIE_ICH
C454
0.1U__16V_04
C462
0.1U__16V_04
3.3VS
Distribute in PCI section
Place within 100 mils
of pin F6 of ICH7 on
the bottom side of
140mils on the top
D10
SCS751V-40
A
C
D11
SCS751V-40
A
C
3.3VS
C544
0.1U__16V_04
1.5VS
C540
0.1U__16V_04
Layout note:
Layout note:
3.3V
C493
1U_X5R_06
C497
0.1U__16V_04
3.3V
VCC5REF
1.5VS
C486
0.1U__16V_04
C524
0.1U__16V_04
1.5VS
Layout note:
Layout note:
C459
0.1U__16V_04
3.3V
3.3V
1.5VS_PCIE_ICH
C447
0.1U__16V_04
3.3V
+
C489
100U_6.3V_B
Place above Caps within 100 mils of ICH on the bottom
side or 140 mils on the top near D28, T28, AD28
C504
0.1U__16V_04
1.5VS
Place within 100mils of
ICH on the bottom side or
140 mils on the top
3.3VS
C495
0.1U__16V_04
Place within 100 mils
of ICH7 on the bottom
side of 140mils on
the top
1.05VS
1.05VS
C490
0.1U__16V_04
Layout note:
5V
5VS
C527
0.1U__16V_04
C455
1U_X5R_06
C482
0.1U__16V_04
C468
*10U_10V_08
C457
10U_10V_08
Place within 100 mils
of pin AD17 of ICH7
on the bottom side or
140 mils on the top
side
1.5VS_PCIE_ICH
L17 HCB1608KF-121T25
1.5VS_PCIE_ICH
C488
0.1U__16V_04
3.3V
C456
0.1U__16V_04
RTCVCC
1.5VS_PCIE_ICH
3.3VS
C500
0.1U__16V_04
Layout note:
3.3VS
1.5VS
1.05VS
C510
0.1U__16V_04
1.5VS_PCIE_ICH
L58
HCB2012KF-500T40
Layout note:
1.5VS_PCIE_ICH
C515
0.1U__16V_04
C450
0.1U__16V_04
C485
1U_X5R_06
Place within 100mils of ICH on the
bottom side or 140 mils on the top
1.5VS
C496
0.1U__16V_04
3.3V
V5REF_SUS
C529
0.1U__16V_04
C491
0.1U__16V_04
Layout note:
C478
0.1U__16V_04
C494
0.1U__16V_04
CLOSE TO C363
C480
0.1U__16V_04
Place within 100 mils
of ICH7 on the bottom
side of 140mils on
the top
CO
R
E
V
CCA
3GP
VCC PAUX
US
B
AT
X
AR
X
ID
E
U
S
B C
O
RE
PCI
U8F
ICH7-M
G10
AD17
F6
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
B27
AG28
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
AD2
AH11
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
C1
AA2
Y7
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
V5
V1
W2
W7
U6
R7
AE23
AE26
AH26
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
W5
P7
A24
C24
D19
D22
G19
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
AB17
AC17
T7
F17
G17
AB8
AC8
K7
C28
G20
A1
H6
H7
J6
J7
E3
V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]
Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]
VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]
VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]
Vcc3_3/VccHDA
VccSus3_3/VccSusHDA
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
VccRTC
VccSus3_3[1]
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
Vcc1_5_A[19]
Vcc1_5_A[20]
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
Vcc1_5_A[24]
Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]
VccSus1_05[3]
Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
VccSus3_3[19]
Layout note:
C458
0.1U__16V_04
C470
0.1U__16V_04
Place at MCH edge
1.05VS
R300
100_04
C463
0.1U__16V_04
C448
0.1U__16V_04
C513
0.1U__16V_04
Place within 100mils of ICH
on the bottom side or 140
mils on the top near pin
AG5