Cirrus Logic CS8420, Руководство пользователя

Страница: 19 / 89

DS245F4 23
CS8420
7.1.4 Channel Status Data Handling
The first 2 bytes of the Channel Status block are decoded into the Receiver Channel Status register. The
setting of the CHS bit in the Channel Status Data Buffer Control register determines whether the channel
status decodes are from the A channel (CHS = 0) or B channel (CHS = 1).
The PRO (professional) bit is extracted directly. Also, for consumer data, the COPY (copyright) bit is ex-
tracted, and the category code and L bits are decoded to determine SCMS status, indicated by the ORIG
(original) bit. Finally, the AUDIO bit is extracted, and used to set an AUDIO indicator, as described in the
Non-Audio Auto Detection section below.
If 50/15 µs pre-emphasis is detected, then this is reflected in the state of the EMPH pin.
The encoded sample word length channel status bits are decoded according to AES3-1992 or IEC 60958.
If the AES3 receiver is the data source for the SRC, then the SRC audio input data is truncated according
to the channel status word length settings. Audio data routed to the serial audio output port is unaffected
by the word length settings; all 24 bits are passed on as received.
“Channel Status and User Data Buffer Management” on page 81 describes the overall handling of CS and
U data.
7.1.5 User Data Handling
The incoming user data is buffered in a user-accessible buffer. Various automatic modes of re-transmit-
ting received U data are provided.
“Channel Status and User Data Buffer Management” on page 81 de-
scribes the overall handling of CS and U data.
Received U data may also be output to the U pin, under the control of a control register bit. Depending on
the data flow and clocking options selected, there may not be a clock available to qualify the U data output.
Figure 19 illustrates the timing.
If the incoming user data bits have been encoded as Q-channel subcode, the data is decoded and pre-
sented in 10 consecutive register locations. An interrupt may be enabled to indicate the decoding of a new
Q-channel block, which may be read via the control port.
RCBL
out
VLRCK
C, U
Output
RCBL and C output are only available in hardware mode 5.
RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CU timing.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If no SRC is used, and the serial audio output port is in master mode, VLRCK = OLRCK.
If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.
C, U transitions are aligned within 1% of VLRCK period to VLRCK edges
±
Figure 19. AES3 Receiver Timing for C & U Pin Output Data