18
DS245F4
CS8420
5.
SAMPLE RATE CONVERTER (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to very high rate
and then downsample to the outgoing rate, resulting in a 24-bit output, regardless of the width of the input. The fil-
tering is designed so that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample
rates are greater than 44.1 kHz. When the output sample rate becomes less than the input sample rate, the input is
automatically band limited to avoid aliasing products in the output. Careful design ensures minimum ripple and dis-
tortion products are added to the incoming signal. The SRC also determines the ratio between the incoming and
outgoing sample rates, and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little
impact on the dynamic performance of the rate converter and has no influence on the output clock.
5.1
Dither
When using the AES3 input, and when using the serial audio input port in Left-Justified and I²S modes, all
input data is treated as 24 bits wide. Any truncation that has been done prior to the CS8420 to less than 24
bits should have been done using an appropriate dither process. If the serial audio input port is used to feed
the SRC, and the port is in Right-Justified mode, then the input data will be truncated to the SIRES bit setting
value. If SIRES bits are set to 16 or 20 bits, and the input data is 24 bits wide, truncation distortion will occur.
Similarly, in any serial audio input port mode, if an inadequate number of bit clocks are entered (say 16 in-
stead of 20), the input words will be truncated, causing truncation distortion at low levels. In summary, there
is no dithering mechanism on the input side of the CS8420, and care must be taken to ensure that no trun-
cation occurs.
Dithering is used internally where appropriate inside the SRC block.
The output side of the SRC can be set to 16, 20, or 24 bits. Optional dithering can be applied, and is auto-
matically scaled to the selected output word length. This dither is not correlated between left and right chan-
nels. It is recommended that the dither control bit be left in its default ON state.
5.2
SRC Locking, Varispeed and the Sample Rate Ratio Register
The SRC calculates the ratio between the input sample rate and the output sample rate and uses this infor-
mation to set up various parameters inside the SRC block. The SRC takes some time to make this calcula-
tion. For a worst case 3:1 to 1:3 input sample rate transition, the SRC will take 9400/Fso to settle (195 ms
at Fso of 48 kHz). For a power-up situation, the SRC will start from 1:1; the worst case time becomes
8300/Fso (172 ms at Fso of 48 kHz).
If the PLL is in use (either AES3 or serial input port), the worst case locking time for the PLL and the SRC
is the sum of each locking time.
If Fsi is changing, for example in a varispeed application, the REUNLOCK interrupt will occur, and the SRC
will track the incoming sample rate. During this tracking mode, the SRC will still rate convert the audio data,
but at increased distortion levels. Once the incoming sample rate is stable, the REUNLOCK interrupt will
become false, and the SRC will return to normal levels of audio quality.
The VFIFO interrupt occurs if the data buffer in the SRC overflows, which can occur if the input sample rate
changes at >10%/second.
Varispeed at Fsi slew rates approaching 10%/sec is only supported when the input is via the serial audio
input port. When using the AES3 input, high frame rate slew rates will cause the PLL to lose lock.
The sample rate ratio is also made available as a register, accessible via the control port. The upper 2 bits
of this register form the integer part of the ratio, while the lower 6 bits form the fractional part. Since, in many
instances Fso is known, this allows the calculation of the incoming sample rate by the host microcontroller.
