Cirrus Logic CS4953xx, Руководство пользователя по оборудованию

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Functional Overview of the CS4953xx Chip
CS4953xx Hardware Users Manual
DS732UM7 Copyright 2008 Cirrus Logic, Inc 1-6
1.2.11 SDRAM Controller
The CS4953xx supports a glueless external SDRAM interface to extend the data memory of the DSP during
runtime. The SDRAM controller provides 2-port access to X and Y memory space, a quad-word read buffer, and a
double-buffered quad-word write buffer. One SDRAM controller port is dedicated to P memory space and the
second port is shared by X and Y memories. The X/Y port has dual write buffers and a single read buffer, and the P
memory port has a single read buffer. One of these buffers is four 32-bit words (128 bits). Every “miss” to the read
buffer will cause the SDRAM controller to burst eight 16-bit reads on the SDRAM interface. The SDRAM
controller supports SDRAMs from 2 MB to 64 MB with various row, bank, and column configurations. The
SDRAM controller runs synchronous to HCLK, the global chip clock.
1.2.12 Flash Controller
The CS4953xx supports a glueless external Flash interface that allows autoboot from a parallel Flash or EEPROM
device extending data memory and/or program memory during DSP runtime. Flash can be accessed using 8-bit, 16-
bit, and 32-bit data modes (1-byte, 2-byte, and 4-byte words) and using an 8-bit or 16-bit data bus, where the word
width is the number of bytes per transfer, and the data bus size is the width of the physical interface to Flash.
Separate chip select pins allow Flash devices to be connected without additional chip select logic. Thus, the interface
supports up to 512k x 16 bits of Flash. The external Flash interface serially accesses the X, Y, and P memory spaces
on the CS4953xx chip.
1.2.13 DMA Controller
The DMA controller contains 12 stereo channels. The O/S uses 11 stereo channels, 6 for the DAO (2 are for the S/
PDIF transmitters), 4 for the DAI, and one for the parallel control port. The addition of the DMA channel for the
parallel control port allows compressed audio data to be input over this port. The DMA block is able to move data to/
from X or Y memory, or alternate between both X and Y memory. The DMA controller moves data to/from X and/or
Y memory opportunistically (if the core is not currently accessing that particular memory space during the current
cycle). The DMA controller has a “Dead Man’s” timer so that if the core is running an inner loop and accessing
memory every cycle, the DMA controller can interrupt the core to run a DMA cycle.
1.2.14 Timers
A 32-bit timer block runs off the CS4953xx DSP clock. The timer count decrements with each clock tick of the DSP
clock when the timer is enabled. When the timer count reaches zero, it is re-initialized, and may be programmed to
generate an interrupt to the DSP.
1.2.15 Clock Manager and PLL
The CS4953xx Clock Manager and PLL module contains an Analog PLL, RTL Clock Synthesizer, and Clock
Manager. The Analog PLL is a customized analog hard macro that contains the Phase Detector (PD), Charge Pump,
Loop Filter, VCO, and other non-digital PLL logic. The Clock Synthesizer is a digital design wrapper around the
analog PLL that allows clock frequency ranges to be programmed. The Clock Manager is a digital design wrapper
for the Clock Synthesizer that provides the logic (control registers) necessary to meet chip clocking requirements.
The Clock Manager and PLL module generates two master clocks:
• HCLK - global chip clock (clocks the DSP core, internal memories, SDRAM, Flash, and all peripherals)
• OVFS - oversampled audio clock. This clock feeds the DAO block which has dividers to generate the
DAO_MCLK, DAO_SCLK, and DAO_LRCLK.
The Clock Manager has the ability to bypass the PLL so that the HCLK will run directly off the PLL Reference
Clock (REFCLK). While operating in this mode, the OVFS clock can still be divided off the VCO so the PLL can be
tested.