Cirrus Logic CS4953xx, Руководство пользователя по оборудованию

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Functional Overview of the CS4953xx Chip
CS4953xx Hardware Users Manual
DS732UM7 Copyright 2008 Cirrus Logic, Inc 1-4
1.2 Functional Overview of the CS4953xx Chip
The CS4953xx chip supports a maximum clock speed of 150 MHz in a 144-pin LQFP or 128-pin LQFP package. A
high-level functional description of the CS4953xx chip is provided in this section.
1.2.1 DSP Core
The CS4953xx DSP core is a pair of general purpose, 32-bit, fixed-point, fully programmable digital signal
processors that achieve high performance through an efficient instruction set and highly parallel architecture. The
device uses two’s complement fractional number representation, and employs busses for two data memory spaces
and one program memory space.
CS4953xx core enhancements include portability of the design, speed improvement, and improvements for
synthesis, verification, and testability. Each member of the CS4953xx family has different SRAM and ROM sizes.
Please refer to the CS4953xx data sheet for details.
1.2.2 Security Extension module
This module is a 64-bit extension module that allows the CS4953xx device to be placed in a secure mode where
decryption is activated via a 128-bit key. This key is written to the security extension in two 64-bit move
instructions. Secure mode is disabled by default, and must be explicitly enabled.
1.2.3 Debug Controller (DBC)
An I
2
C slave debug controller (DBC) is integrated within the CS4953xx DSP core. Two pins are reserved for
connecting a PC host to the debug ports on either DSP. The debug port consists of two modules, an I
2
C slave and a
debug master. The DBC master sends dedicated signals into the DSP core to initiate debug actions and it receives
acknowledge signals from the core to indicate the requested action has been taken. Basically, this interface allows
the DBC to insert instructions into the pipeline. The core will acknowledge the action when it determines the
pipeline is in the appropriate state for the inserted action to be taken.
1.2.4 Digital Audio Output (DAO1, DAO2) Controller
The CS4953xx has two Digital Audio Output (DAO) controllers, each of which contains 4 stereo output ports. One
port on each DAO can be used as a S/PDIF transmitter. The DAO ports can transmit up to 16 channels of audio
sample data in I
2
S-compatible format. The audio samples are stored in 16 channel buffers which are 32 bits wide.
Four of the channels can also serve as output buffers for the two S/PDIF transmitters. The O/S can dedicate DMA
channels to fill the DAO data buffers from memory. DAO control is handled through the peripheral bus.
1.2.5 Digital Audio Input (DAI1) Controller
The CS4953xx Digital Audio Input (DAI) controller has four stereo input ports and DAI control is handled through
the peripheral bus. Each DAI pin can be configured to load audio samples in a variety of formats. In addition to
accepting multiple formats, the DAI controller has the ability to accept multiple stereo channels on a single
DAI1_DATAx pin. All four DAI pins are slaves and normally share the same serial input clock pins (DAI1_SCLK
and DAI1_LRCLK). Pins DAI1_DATA[3:0] may also be reconfigured to use the DAO serial input clock pins
(DAOx_SCLK and DAOx_LRCLK). A single global configuration register provides a set of enable bits to ensure
that ports may be started synchronously.
1.2.6 Compressed Data Input / Digital Audio Input (DAI2) Controller
The DAI2 controller has one input port and its own SCLK and LRCLK and can be used for accepting PCM data in
the same way as DAI1, but is used primarily for the delivery of compressed data. When configured for compressed
data input, custom internal hardware is enabled that off-loads some pre-processing of the incoming stream to help
maximize the MIPS available in the DSP core for user-customized applications.