Cirrus Logic Crystal LAN CS8900A, Лист данных продукта

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DS271PP3 25
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
location is written into the EEPROM Data register.
If the command is an Erase or Erase-All, no data is
transferred to or from the EEPROM Data register.
Before issuing any command, the host must wait
for the SIBUSY bit (Register 16, SelfST, bit 8) to
clear. After each command has been issued, the
host must wait again for SIBUSY to clear.
3.5.3 Enabling Access to the EEPROM
The Erase/Write Enable command provides protec-
tion from accidental writes to the EEPROM. The
host must write an Erase/Write Enable command
before it attempts to write to or erase any EEPROM
memory location. Once the host has finished alter-
ing the contents of the EEPROM, it must write an
Erase/Write Disable command to prevent unwant-
ed modification of the EEPROM.
3.5.4 Writing and Erasing the EEPROM
To write data to the EEPROM, the host must exe-
cute the following series of commands:
1) Issue an Erase/Write Enable command.
2) Load the data into the EEPROM Data register.
3) Issue a Write command.
4) Issue an Erase/Write Disable command.
During the Erase command, the CS8900A writes
FFh to the specified EEPROM location. During the
Erase-All command, the CS8900A writes FFh to
all locations.
3.6 Boot PROM Operation
The CS8900A supports an optional Boot PROM
used to store code for remote booting from a net-
work server.
3.6.1 Accessing the Boot PROM
To retrieve the data stored in the Boot PROM, the
host issues a Read command to the Boot PROM as
a Memory space access. The CS8900A decodes the
command and drives the CSOUT pin low, causing
the data stored in the Boot PROM to be shifted into
the bus transceiver. The bus transceiver then drives
the data out onto the ISA bus.
3.6.2 Configuring the CS8900A for Boot PROM
Operation
Figure 6 shows how the CS8900A should be con-
nected to the Boot PROM and ’245 driver. To con-
figure the CS8900A’s internal registers for Boot
PROM operation, the Boot PROM Base Address
must be loaded into the Boot PROM Base Address
register (PacketPage base + 0030h) and the Boot
PROM Address Mask must be loaded into the
Command Opcode
(bits 9,8)
EEPROM Address
(bits 7 to 0)
Data EEPROM Type Execution
Time
Read Register 1,0 word address yes all 25 µs
Write Register 0,1 word address yes all 10 ms
Erase Register 1.1 word address no all 10 ms
Erase/Write Enable 0,0 XX11-XXXX no ‘CS46, ‘C46 9 µs
11XX-XXXX no ‘CS56, ‘C56, ‘CS66, ‘C66 9 µs
Erase/Write Disable 0,0
0,0 XX00-XXXX no ‘CS46, ‘C46 9 µs
00XX-XXXX no ‘CS56, ‘C56, ‘CS66, ‘C66 9 µs
Erase-All Registers 0,0
0,0 XX10-XXXX no ‘CS46, ‘C46 10 ms
10XX-XXXX no ‘CS56, ‘C56, ‘CS66, ‘C66 9 µs
Write-All Register 0,0
0,0 XX01-XXXX yes ‘CS46, ‘C46 10 ms
01XX-XXXX yes ‘CS56, ‘C56, ‘CS66, ‘C66 10 ms
Table 7. EEPROM Commands