20
DS851DB1
CDB42L56
J2
HPOUTA FLT/NOFLT
Selects filtered or unfiltered output
for HPOUTA
*2 - 4, *1 - 3
Unfiltered output selected for HPOUTA.
4 - 6, 3 - 5
RC filtered output selected for HPOUTA.
J3
HPOUTB FLT/NOFLT
Selects filtered or unfiltered output
for HPOUTB
*2 - 4, *1 - 3
Unfiltered output selected for HPOUTB.
4 - 6, 3 - 5
RC filtered output selected for HPOUTB.
J34
Board Power
Selects source of Board Power
1 - 2
Board powered from ex5 V source con-
nected to TP9/TP10.
*2 - 3
Board powered from USB.
J16
Tri-state I/O
Tri-states FGPA I/O
SHUNTED
FGPA I/O pins are tri-stated.
*OPEN
FGPA I/O pins in normal operation.
*Default factory settings
Table 3. Jumper Settings
Содержание CDB42L56
Страница 28: ...28 DS851DB1 CDB42L56 8 CDB42L56 SCHEMATICS Figure 35 CS42L56 Analog I O Schematic Sheet 1 ...
Страница 29: ...DS851DB1 29 CDB42L56 Figure 36 S PDIF Digital Interface Schematic Sheet 2 ...
Страница 30: ...30 DS851DB1 CDB42L56 Figure 37 PLL oscillator and external I O connections Schematic Sheet 3 ...
Страница 31: ...DS851DB1 31 CDB42L56 Figure 38 Microcontroller and FPGA Schematic Sheet 4 ...
Страница 32: ...DS851DB1 32 CDB42L56 Figure 39 Power Schematic Sheet 5 ...
Страница 33: ...DS851DB1 33 CDB42L56 9 CDB42L56 LAYOUT Figure 40 Silk Screen ...
Страница 34: ...DS851DB1 34 CDB42L56 Figure 41 Top Side Layer ...
Страница 35: ...DS851DB1 35 CDB42L56 Figure 42 GND Layer 2 ...
Страница 36: ...DS851DB1 36 CDB42L56 Figure 43 Power Layer 3 ...
Страница 37: ...DS851DB1 37 CDB42L56 Figure 44 Bottom Side Layer ...