17
Award BIOS Setup Program
Item Help
Menu Level
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
3-3 Advanced Chipset Features
By choosing the Advanced Chipset Features option from the CMOS Setup Utility
menu (Figure 3-1), the screen below is displayed. This sample screen contains the
manufacturer's default values for the mainboard.
All of the above settings have been determined by the mainboard manufacturer
and should not be changed unless you are absolutely sure of what you are
doing. Explanation of the DRAM timing and chipset features setup is lengthy,
highly technical and beyond the scope of this manual. Below are some
abbreviated descriptions of the functions in this setup menu.
A. DRAM Clock/Drive Control
DRAM Timing
The function allows you to enable or disable the DRAM timing by SPD. When set
to Manual, you can select the DRAM CAS Latency, SDRAM Cycle Length and Bank
Interleave configuration.
B. Flash BIOS Protection
The mainboard manufacturer developed BIOS protection technology that protects
the System BIOS from accidental corruption by unauthorized users or computer
viruses. When enabled, the BIOS data cannot be changed when attempting to
update BIOS with the the FLASH utility. When disabled, the BIOS data can be
updated by using the FLASH utility.
Press Enter
Press Enter
Press Enter
Disabled
Disabled
Disabled
Disabled
DRAM Clock/Drive Control
AGP & P2P Bridge Control
CPU & PCI Bus Control
Memory Hole
System BIOS Cacheable
Video RAM Cacheable
Flash BIOS Protection
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Figure 3-4 Chipset Features Setup Screen
