User's Manual
26
3-3 Advanced Chipset Features
By choosing the Advanced Chipset Features option from the CMOS Setup Utility
menu (Figure 3-1), the screen below is displayed. This sample screen is for referrence
use only.
All of the above settings have been determined by the mainboard manufacturer
and should not be changed unless you are absolutely sure of what you are
doing. Explanation of the DRAM timing and chipset features setup is lengthy,
highly technical and beyond the scope of this manual. Below are abbreviated
descriptions of the functions in this setup menu. You can look on the world
wide web for helpful chipset and RAM configuration information including
AWARD's web site at http://www.award.com.
A.
A.
A.
A.
A.
SDRAM Cycle Length
SDRAM Cycle Length
SDRAM Cycle Length
SDRAM Cycle Length
SDRAM Cycle Length
When synchronous DRAM is installed, the number of the clock cycles of CAS
latency depends on the DRAM timing. Do not reset this setting from the default
value specified by the system designer.
Figure 3-4 Advanced Chipset Features Setup Screen
Item Help
Menu Level
DRAM Timing By SPD
X DRAM Clock
X SDRAM Cycle Length
X Bank Interleave
Memory Hole
PCI Master Pipeline Req
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP Mode
AGP Driving Control
X AGP Driving Value
AGP Fast Write
Flash BIOS Protection
OnChip Sound
OnChip Modem
CPU to PCI Write Buffer
Phoenix - AwardBIOS CMOS Setup Utility
Phoenix - AwardBIOS CMOS Setup Utility
Phoenix - AwardBIOS CMOS Setup Utility
Phoenix - AwardBIOS CMOS Setup Utility
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Advanced Chipset Features
Advanced Chipset Features
Advanced Chipset Features
Advanced Chipset Features
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Enabled
133M
3
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
Disabled
64M
4X
Auto
D A
Disabled
Disabled
Auto
Auto
Enabled
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