CHAINTECH 6VIV, Руководство пользователя

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User's Manual
26
3-3 Advance Chipset Features
By choosing the Advanced Chipset Features option from the Standard CMOS
Features menu (Figure 3-1), the screen below is displayed. This sample screen
contains the manufacturer's default values for the mainboard.
All of the above settings have been determined by the mainboard manufacturer
and should not be changed unless you are absolutely sure of what you are
doing. Explanation of the DRAM timing and chipset features setup is lengthy,
highly technical and beyond the scope of this manual. Below are abbreviated
descriptions of the functions in this setup menu. You can look on the world
wide web for helpful chipset and RAM configuration information including
AWARD's web site at http://www.award.com.
A. BANK 0/1 & 2/3 DRAM Timing
This item allows you to select the value in this field, depending on whether the
board has paged DRAM or EDO (Extended Data Output) DRAMs.
B. SDRAM Cycle Length
When synchronous DRAM is installed, the number of the clock cycles of CAS
latency depends on the DRAM timing. Do not reset this setting from the default
value specified by the system designer.
Figure 3-4 Chipset Features Setup Screen
Item Help
Menu Level
Bank 0/1 DRAM Timing SDRAM 8/10ns
Bank 2/3 DRAM Timing SDRAM 8/10ns
SDRAM Cycle Length 3
DRAM Clock Host CLK
Memory Hole Disabled
P2C/C2P Concurrency Enabled
System BIOS Cacheable Disabled
Video RAM Cacheable Disabled
AGP Aperture Size 64M
AGP-4X Mode Disabled
AGP Driving Control Auto
X AGP Driving Value DA
AGP Fast Write Disabled
Flash BIOS Protection Disabled
OnChip Sound Auto
OnChip modem Auto
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Enabled
CMOS Setup Utility- Copyright (C) 1984-2000 Award Software
Advanced Chipset Features
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults