CHAPTER 2
2 - 16
COPYRIGHT
2000 CANON INC. CANOSCAN N650U/N656U/N1220U REV.0 JUNE 2000 PRINTED IN JAPAN (IMPRIME AU JAPON)
D. Drive Motor Control Circuit
Figure 2-14 shows a block diagram of the drive motor control circuit. The control program
analyzes each command sent from the host computer and sends a command to generate motor
clock to the gate array. The gate array generates the four phase motor drive pulse signals
(MA+, MA-, MB+, MB-), which are sent to the drive motor via the motor driver.
When the host computer changes the resolution, the control program sets to change the
frequency of the motor drive pulse signals for the gate array, then changes the rotating speed
of the drive motor.
Figure 2-14
MA+
MB-
MB+
MA-
Main PCB
Drive motor
M1
Host computer
Gate array
Motor
driver
PA+
PB-
PB+
PA-
J2-1
-2
-3
-4
Control program
