C&T Solution CT-MHW0X, Руководство пользователя

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CT-MHW0X Intel 4th Gen Core Processor i7/i5/i3/Pentium/Celeron Micro-ATX IMB
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Signal I/O Description
MDI[0:3]+
MDI[0:3]-
I/O
Gigabit Ethernet Controller 0: Media Dependent
Interface Differential Pairs 0, 1, 2, 3. The MDI
can operate in 1000, 100 and 10 Mbit/sec
modes. Some pairs are unused in some modes,
per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
4.11 LPC
The LPC interface provides legacy I/O support.
Signal I/O Description
LPC_AD[0:3] I/O
LPC multiplexed address, command and data
bus
LPC_FRAME# O
LPC frame indicates the start of an LPC cycle
4.12 Testability Signals (JTAG)
Signal I/O Description
TDO OD
Test Data Output: TDO is the serial output for
test instructions and data from the test logic
defined in this standard.
TDI I
Test Data Input: Serial test instructions and data
are received by the test logic at TDI.
TMS I
Test Mode Select: The signal is decoded by the
Test Access Port (TAP) controller to control test
operations.
TCK I
Test Clock Input: The test clock input provides
the clock for JTAG test logic.
4.13 General Purpose Input Output
GPI and GPO pins may be implemented as GPIO (Module specific). GPI and
GPO pins may be implemented as GPIO.