Pileup Rejector
As count rates increase, the possibility of peak pileup, a peak’s amplitude being dis-
torted by a succeeding pulse, increases. PUR logic, which can be enabled through the
computer interface, will prevent SCA outputs if there is peak pileup. With this logic
enabled, the outputs of the Fast Discriminator, and the LLD, ULD and Peak signals are
used. Figure illustrates the various possibilities. As explained in the previous section,
for an SCA signal to be generated, there must be an LLD crossing, then a Peak detec-
tion without a ULD. Assuming that all of the inputs meet these prior conditions:
1.
Peak signals 1 and 2 will cause an SCA pulse because there was only a single
Fast Discriminator pulse between them.
2.
Peak Signal 3 will not generate an SCA pulse because more than one FDO
was recorded between peaks 2 and 3.
3.
Peak 4 shows the condition when multiple inputs are received but cannot be
resolved by the Fast Discriminator circuits. This results in a single FDO and
an SCA.
Implicit to this discussion is that the Reject logic is initialized (cleared) shortly after
the PEAK* edge, as shown in the timing diagram in Figure 21.
30
Circuit Description
Figure 21 PUR Timing Diagram
