CAMERA LINK vieworks LVC-25MC2-30, Руководство пользователя

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VC Camera Link series
Page 14 of 86 RA14-11A-010
5.3 Camera Block Diagram
CMOS
Sensor
Image
Processing
And
Control
Logic
MicroController
DDR2
FLASH SRAM
Ext. Trig
Strobe
C
a
m
e
ra
L
in
k
F
u
ll
C
o
n
fig
u
ra
tio
n
FPGA
16 / 32 Channel
LVDS Image Data
SPI Control
EEPROM
Figure 5.1 Camera Block Diagram
All controls and data processing of VC cameras are carried out in one FPGA chip. The FPGA generally consists
of a 32 bit RISC Micro-Controller and Processing & Control Logic. The Micro-Controller receives commands from
the user through the Camera Link interface and then processes them. The Processing & Control Logic
processes the image data received from the CMOS sensor and then transmits data through the Camera Link
interface. And also, the Processing & Control Logic controls the trigger inputs and strobe outputs which are
sensitive to time. Furthermore, FLASH and DDR2 is installed outside FPGA. DDR2 is used to process images
and FLASH contains the firmware that operates the Micro-Controller.