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8. Timing Chart
●
Pixel clock timing (common in various operation modes)
[Phase relationship between clock output and data]
(Note) The above timing represents the signal timing before being encoded to serial data by the channel link device on the
side of the sending end (the part circled in the above right figure). If signal conversion from serial to parallel is made by
a channel link device in accordance with the Camera Link standard on the side of the receiving end, the phase
relationship between the clock and the data after decoding will be different from that of the above timing due to the
structural nature of a channel link device. (In the case of the output from a channel link device, the data are aligned
with the trailing edge of the clock signal.)
(!) FS5000HECL does not have the timing signal “BUSY” that LVDS type FC cameras normally have.
(Note) When a channel link device is mounted directly to the capture interface on the user side, instead of using a
commercially available capture board that supports Camera Link, it is necessary to pay close attention to the
descriptions of the data sheet of the channel link device including the phase relationship between data and clock prior to
the use.
●
Horizontal timing
HD
CCD output signal
OB
approx.
４． ５
Dummy
bit
OB
４０
４６０
２８
１２
１
３ １６
Effective p ixe ls
２６ １ ６
５４０
1
hor izonta l p eriod(
1
H)
２
４
３
５
２
６１
６
(Interna l hor izonta l
synchronous s ign al)
３ １ ５ ６
２
６
１
６
２ ７ ３
１
２
４
３
５
４ ３
２
６
１
６
５ ０ ８
Effective imag e durat ion
Ｏ Ｂ （ ４ ０ ）
Ｏ Ｂ （ １ ２ ）
LDV
Imagesignal
( Dig ita l)
Internal
signal
Image
output
Effective ima ge du rat io n(
２６ １ ６
)
In e
ffective imag e durat ion (
５ ４ ０
)
H ori zo nta l tra ns fer
s usp en sio n tim e
* Unless otherwise specified, the time unit of the numbers in the horizontal timing chart is CLK (= 1/32.5MHz = 30.77nS).
Col or coding（Horiz ontal output tim ing）
ＣＣＤ output signal
１
Ｅ ｆ ｆ ｅ ｃ ｔ ｉ ｖ ｅ
ｐ ｉ ｘ ｃ ｅ ｌ ｓ
２ ６ １ ６
２
４
３
５
（Odd line）
R G R G R
R G
R G
２
６
１
６
２
６
１
５
G R G R
R G
R G
G
（Even line）
G B G B
B
B G
G B G B
B G
B G
B G
G
１
Ｅ ｆ ｆ ｅ ｃ ｔ ｉ ｖ ｅ
ｐ ｉ ｘ ｃ ｅ ｌ ｓ
２ ６ １ ６
２
４
３
５
２
６
１
６
２
６
１
５
ＣＣＤ output signal
1 CL K=
30 .77
n S
10 ns( max)
Clock o utp ut
Digital data
10 b it
or
8 bit
CLK
A/D
10
b it
Camera L ink
connector
C
h
a
n
n
e
l
L
in
k
(LDV,FDV)
C
a
m
e
ra
L
in
k
B
a
s
e
C
o
n
fi
g
ra
ti
o
n
P CL K
CLK
DEMULTI PLE X
.
