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Document type: 

Title: 

Revision date: 

Revision: 

User's Manual (MUT) 

Mod. V977 16 Channel I/O Register (Status A) 

27/08/2004 

 

  

NPO: 

Filename: 

Number of pages:  Page: 

00118/01:V977X.MUTX/01 

V977_REV1.DOC 

21 

 

3.   Operating modes 

3.1.  Functional description 

The Mod. V977 is a 16 channel general purpose I/O Register or as Multihit Pattern Unit 
The following figure shows the simplified scheme of a single channel: 
 

OUTPUT

CH #n

OUTPUT

OR

OUTPUT

OR

TO IRQ

LOGIC

INPUT

CH #n

INPUT READ

VME REGISTER

CONTROL

REGISTER

PATTERN BIT

INPUT

GATE

INPUT MASK

VME REGISTER

INPUT SET

VME REGISTER

CONTROL
REGISTER

GATE MASK BIT

1

0

D

Q

AR

1

D

Q

AR

SINGLE HIT READ

VME REGISTER

MULTIHIT READ

VME REGISTER

1

0

OUTPUT MASK
VME REGISTER

OUTPUT SET

VME REGISTER

1

0

CONTROL
REGISTER

OR MASK BIT

INTERRUPT MASK

VME REGISTER

FROM TEST

CHANNEL

LOGIC

CLEAR OUTPUT

VME REGISTER

INPUT

CLEAR

AR

 

Fig. 3.1: Mod. V977 channel structure 

The core of each channel is composed by a couple of FLIP -FLOPs, which perform the 
memory functions. The two cascaded FLIP -FLOPs, as shown in Fig. 3.1, allow to detect 
the following events: none, one or two input hits. The FLIP-FLOPs status of all channels 
can be read via VME, in the SINGLEHIT READ REGISTER and MULTIHIT READ 
REGISTER, which are related respectively to the first and to the second cascaded 
FLIP_FLOP. The content of such register can also be read by accessing the SINGLEHIT 
READ-CLEAR REGISTER and MULTIHIT READ-CLEAR REGISTER: in this case the 
FLIP -FLOPs are cleared after readout.  
The FLIP-FLOPs of all channels can also be cleared both via VME, by accessing the 
CLEAR OUTPUT REGISTER, and via the front panel CLEAR signal.  
The FLIP FLOPs are set either via an input hit or via VME write access (INPUT SET 
REGISTER). By accessing the CLEAR OUTPUT REGISTER, the INPUT SET 
REGISTER is cleared. 
The capabilty of receiving input hits can be masked via VME through the INPUT MASK 
REGISTER (individually for each channel), or via the input GATE signal (common to all 
channels), which can be masked in its turn.  
The status of the inputs can also be read directly vi a VME in the INPUT READ 
REGISTER. 
The status of the channel LEDs and of the outputs depend on the module’s programming. 

 

Содержание V977

Страница 1: ...Technical Information Manual MOD V977 27 August 2004 Revision n 1 16 CHANNEL I O Register Status A MANUAL REV 1 NPO 00118 01 V977X MUTX 01...

Страница 2: ...he User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It i...

Страница 3: ...TECHNICAL SPECIFICATION TABLES 7 2 6 FRONT PANEL 8 3 OPERATING MODES 9 3 1 FUNCTIONAL DESCRIPTION 9 3 1 1 I O register mode 10 3 1 2 Multihit pattern unit mode 10 3 1 3 Test channel 11 3 2 OR LOGIC 1...

Страница 4: ...ERRUPT VECTOR 19 4 17 SERIAL NUMBER 19 4 18 FIRMWARE REVISION 19 4 19 CONTROL REGISTER 19 4 20 DUMMY16 20 4 21 SOFTWARE RESET 20 REFERENCES 21 LIST OF FIGURES FIG 2 1 MOD V977 FRONT PANEL 8 FIG 3 1 MO...

Страница 5: ...t panel pushbutton The TEST output signal can be either NIM or TTL selected with the same on board switch of the channels output Input signals can be individually masked via VME or globally via a fron...

Страница 6: ...IM or TTL LEMO 00 50 impedance 2 OR and NOT OR OUTPUT NIM or TTL selectable LEMO 00 LEDS Name Function Color 16 I O STATUS Depends on the module s programming status see 3 1 Green 16 I O STATUS Depend...

Страница 7: ...ess selection No 1 jumper for the output signal type selection up NIM down TTL 2 4 Power requirements Table 2 1 Power requirements Power supply Current absorption 5 V 2 3A 2 5 Technical specification...

Страница 8: ...27 08 2004 1 NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977_REV1 DOC 21 8 2 6 Front Panel Fig 2 1 Mod V977 Front Panel Mod V977 16 CH STATUS A I O REGISTER PATTERN UNIT CLR DTACK TST O...

Страница 9: ...ons The two cascaded FLIP FLOPs as shown in Fig 3 1 allow to detect the following events none one or two input hits The FLIP FLOPs status of all channels can be read via VME in the SINGLEHIT READ REGI...

Страница 10: ...READ VME REGISTER OUTPUT MASK VME REGISTER OUTPUT SET VMEREGISTER CLEAR OUTPUT VME REGISTER INPUT CLEAR AR Fig 3 2 I O register mode In this operating mode the output of one channel is active when a s...

Страница 11: ...3 Multihit pattern unit mode In this operating mode the output of one channel is active when a double hit from front panel or VME generated is present The output can also be set by a write access to...

Страница 12: ...as front panel signals and can be eventually masked Also the TEST signal participates to the OR logic it can also be masked 3 3 Interrupter capability The Mod V977 house a VME INTERRUPTER The module...

Страница 13: ...nual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 1 NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977_REV1 DOC 21 13 IRQ 1 IRQ7 FROM CHANNELS LOGIC FROM TEST CHANNEL LOGIC INTE...

Страница 14: ...e accessible in D16 mode Table 4 1 Address Map for the Mod V977 ADDRESS REGISTER CONTENT ADDR DATA R W Base 0000 Base 0002 Base 0004 Base 0006 Base 0008 Base 000A Base 000C Base 000E Base 0010 Base 00...

Страница 15: ...he relevant channel FLIP FLOP see 3 1 is set regardless the corresponding input connector s status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INPUT SET In Multihit pattern unit mode this register allows to...

Страница 16: ...onds to one channel it reproduces the relevant input connector s logic level regardless the INPUT MASK register s status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INPUT READ 4 6 Single hit read register B...

Страница 17: ...nt output is masked and no output signal is produced regardless the FLIP FLOPs status The output signal can be produced anyway via the relevant bit in the OUTPUT SET register see 4 8 15 14 13 12 11 10...

Страница 18: ...egister clears the second FLIP FLOP see 3 1 of all channels 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MULTIHIT READ CLEAR 4 14 Test control register Base address 001A read write This register handles all...

Страница 19: ...r Base address 0022 read write This register contains the STATUS ID that the V977 places on the VME data bus during the interrupt acknowledge cycle Bits 8 to 15 are meaningless 15 14 13 12 11 10 9 8 7...

Страница 20: ...sent via FRONT PANEL signal is masked default setting 0 the GATE sent via FRONT PANEL signal is enabled incoming hits are accepted only as the GATE is active OR MASK read write 0 the OR and OR FRONT...

Страница 21: ...nel I O Register Status A 27 08 2004 1 NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977_REV1 DOC 21 21 References 1 VMEbus Specification Manual Revision C 1 October 1985 2 VMEBus for Phys...

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