BVM PMCCTR32, Руководство пользователя

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PMCCTR32
16
Copyright

2001 BVM Ltd.
7.3.13.5 Internal Counter/Timer Clock/De-bounce (Bit 10..8: INCLK2..0)
These bits set the clock frequency for the Counter/Timers when selected as internally clocked - see
section "7.3.10 Counter/Timer Clock Source Register (on page 15)". These bits also set the de-
bounce period as shown below when clocked internally or externally.
INCLK0-2 Clock Frequency De-bounce Period
0 260kHz
2
µ
S
1 130kHz
4
µ
S
2 65kHz
8
µ
S
3 32kHz
15
µ
S
4 16kHz
31
µ
S
5 8kHz
61
µ
S
6 4kHz
120
µ
S
7 2kHz
250
µ
S
7.3.14 Watchdog Trigger Register
The 8-bit read/write Watchdog Trigger Register must be written to with bit 0 set to 0 and 1 alternately
within
±
25% of the watchdog refresh time when the watchdog function is enabled in the Status &
Control Register - see section "7.3.13 Status & Control Register (on page 15)".
7.3.15 Watchdog Timer Register
The 8-bit read/write Watchdog Timer Register is used to set the refresh period. The watchdog timer
runs from its own independent 32.768kHz oscillator and has a programmable refresh period between
125ms and 2sec. On reset the watchdog is not running and has a refresh period of 125ms. The
watchdog timer is started by the first write to the watchdog trigger register. Bits 2 - 0 set the refresh
period, bits 7 - 3 are undefined on a read and should be written as zero for future compatibility.
Note that once the internal watchdog is running, this register is read only - writing to the register will
cause the watchdog to trigger.
Bits
2 - 0 Watchdog Refresh Period
0 125ms
1 250ms
2 500ms
3 1.0sec
4 2.0sec
5 2.0sec
6 2.0sec
7 2.0sec