3424-XX-UM
ProDAQ 3424 Function Card User Manual
Page 26 of 56
Copyright,
1998-2005 Bustec Production Ltd.
The 3424 is able to work in the stand-alone mode or in multiple-card synchronization mode.
The multiple-card synchronization mode is used in the case when all 3424 boards have to sample
the input signal simultaneously and when Data Acquisition has to start in the same time on all of
them.
The 3424 can be set as a Master (MASTER bit in FCCSR register set) or Slave (MASTER bit
cleared). If 3424 works in a stand-alone mode then it has to be always a Master. If the group of the
3424 boards work in a multiple-card synchronization mode then only one function card can be set
as a Master and all others as a Slaves.
The Master generates two signals that have to be distributed to all Slaves: clock signal and
SYNC/TRIG signal.
The clock signal can be distributed as a PLL reference clock (2 MHz low frequency signal
multiplied then in the PLL to 125 MHz for DDS circuitry) or as a sampling clock applied directly to
the ADCs (5.12 MHz to 13.824 MHz). Depending on the selected clock signal, proper settings on
the Slaves have to be done.
The Master is able to send the clock signal to the following outputs:
1) PLL reference clock
Trigger output, stack B
Front panel clock output
2) ADC clock
Local synchronization link clock line
Front panel clock output
The configuration of the Master where the reference clock is send to the trigger output and the
ADC clock is send to the local synchronization and/or front panel clock outputs is allowed.
The second signal generated by the Master is SYNC/TRIG signal. It is used to synchronize all
ADCs and start Data Acquisition at the same time. The SYNC/TRIG events are described in Table
6.
PHASE
EVENT
CONDITION
PULSE
P1
update of the DDS
– this pulse
is used by the boards which
receive PLL reference clock
Occurs only if the board
armed together with the
SYNC_NEED bit set
P1, width of 200ns
P2
reset and settling of the ADCs
– this pulse resets ADCs and
ensures the settling time of the
FIR filters
Occurs only if the board
armed together with the
SYNC_NEED bit set
P2, width of approx.
896ms, synchronized to
the falling edge of the
ADC clock
P3
start of the Data Acquisition
–
this pulse tells the Slave to start
Data Acquisition (go to pre/post
trigger or wait for the start/stop
trigger events, depending on the
settings)
Always present
P3, width of 5 ADC
clocks, synchronized to
the falling edge of the
ADC clock
P4
start trigger event
– this pulse
tells the Slaves to go to the post
trigger
Occurs if the start on
trigger selected on the
Master and start trigger
event happens
P4, width of 2 ADC
clocks, synchronized to
the falling edge of the
ADC clock
P5
stop trigger event
– this pulse
tells the Slaves to finish post
trigger
Occurs if the stop on
trigger selected on the
Master and stop trigger
event happens
P5, width of 2 ADC
clocks, synchronized to
the falling edge of the
ADC clock
Table 6
– SYNC/TRIG signal events
