Bustec ProDAQ 3411, Руководство пользователя

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3411-XX-UM ProDAQ 3411 24-Ch. ADC Function Card User Manual
Page 34 of 40 Copyright,
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1998-2009 Bustec Production Ltd.
A.1.5 ITRI Register
Configures the input trigger of the function card.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Operation
-- -- -- -- RW RW RW RE RW RW RW -- -- -- -- --
Initial
X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Content n/u not used POL FPo Edge FPin SWT MBT DIVC not used
DIVC Writing a one (“1”) to this bit enables the sample clock as specified in the DIVCLK register as
a source for the input trigger.
MBT Enables the input trigger from the motherboard as a source for the input trigger.
SWT Writing a one (“1”) to this bit activates the input trigger (Software Trigger).
FPin Enables trigger from front panel
Edge
always zero (“0”)
FPo
Enables trigger output to the front panel
POL
Sets the polarity of the output.
A.1.6 DIVCLK Register
This register holds the divider value for deriving the sample clock from the internal clock source.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Operation RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Initial
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Content DIVCLK DELAY
DELAY defines the time between the input multiplexer switching to the next channel and the ADC
start. Valid range is 2...255 resulting in the following ranges (depending on the setting of the
DSC field in the MODE register):
DSC Range
1.6 µs 3.2 µs to 408.0 µs
25.6 µs 51.2 µs to 6528 µs
409.6 µs 819.2 µs to 104.448 ms
6553.6 µs 13.1072 ms to 1671.168 ms
DIVCLK Base clock selection for the data acquisition (scanning). The valid range is 2...255 resulting in
the following ranges (depending on the CSC field in the MODE register:
CSC Range
3.2 µs 9.6 µs to 819.2 µs
102.4 µs 307.2 µs to 26214.2 µs