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ProDAQ 3411 24-Ch. ADC Function Card User Manual
3411-XX-UM
Copyright,
1998-2009 Bustec Production Ltd.
Page 33 of 40
A.1.3 FCLEN Register
Specifies the FIFO size in words.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Operation RO RO
RO
RO
RO
RO
RO
RO
RO
RO
RO RO
RO RO
RO
RO
Initial
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Content
FIFO size
3411-AA: 0x0800 (2048 words)
3411-AB: 0x4000 (16384 words)
A.1.4 OTRI Register
Register to configure the output trigger.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Operation
--
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Initial
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Content
n/u
inSelect
Pol FPo OMP OMB SWT MBT DivC iSel
ADC
conv
DAQ
start FPin
FPin
A one (“1”) selects the front panel trigger input as the source
ADCconv
A one (“1”) enables the start of the conversion to generate a signal
DAQstart
A one (“1”) enables the start of the acquisition to generate a signal
iSel
A one (“1”) enables the internal trigger selector
DivC
A one (“1”) enables the system clock divider as the trigger source
MBT
A one (“1”) enables the trigger from the motherboard
SWT
software trigger
OMB
A one (“1”) enables the trigger output to the motherboard as a level
OMP
A one (“1”) enables the trigger output pulse to the motherboard.
FPo
A one (“1”) enables trigger to the front panel
Pol
allows to change the polarity of the output. A one (“1”) selects an active high output, while a
zero (“0”) select an active low output.
inSelect
allows selection of the trigger output one of the following internal sources
Value
Source enabled
0
Data acquisition ready
1
Repeat counter is zero
2
FIFO full
3
FIFO almost full
4
FIFO almost empty
5
FIFO half full
6
ADC ready
7
Receptive mode counter pulse