Bustec ProDAQ 3120, Руководство по оборудованию

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3120-XX-HM ProDAQ 3120 Standard Motherboard Hardware Manual
Page
12 of 28 Copyright, © Bustec Production Ltd.
A central feature of the MB is the trigger interface, which is built around a switch matrix allowing
1:n and m:1 (m, n = 1 to 24) connections. The VXIbus ECL and TTL trigger lines can be switched
individually to the function cards. Triggers can be sent from the function cards to the VXIbus TTL
trigger lines or to other function cards. It is possible to request VXIbus intercept by help of the VXI
interface.
The function card address space is directly mapped into the VXIbus address space of the ProDAQ
module, allowing control programs to access the function card registers easily. In addition to the
single access, common actions to the function card can be initiated using multicast or broadcast
operation. For this purpose special address regions of the motherboard have to be used. Multicast
write operations will send the same data word to the function cards. In this mask register the set of
function cards involved in the multicast operation is set in a mask register found in the VXI
configuration area. The ProDAQ bus of this motherboard supports also the read of two function
cards in parallel, if long word accesses are used.
4.1
Accessing the Motherboard
4.1.1 Supported Access Types
The VXIbus Interface conforms to the VXIbus specification issue 1.4. In addition to a static VXI
device configuration, it supports dynamic configuration. It is a register based VXIbus device, which
supports A16/A32 addressing, and requires 16 Mbytes from the A32 address space. With a
jumper, J1, the module can be configured as an A16/A24 bit device, occupying 4 Mbytes of the
A24 address space.
The module responds to the following AM codes:
AM = 0x29 or 0x2d short IO (A16) for access of VXIbus configuration registers.
AM = 0x0e or 0x0d or 0x0a or 0x09 normal A32 access
AM = 0x3e or 0x3d or 0x3a or 0x39 normal A24 access
AM = 0x0b or 0x0f for A32 block transfers
AM = 0x3b or 0x3f for A24 block transfers
The module can be accessed with byte D08(EO), word (D16) and long word (D32) transfers.
Unaligned data transfer, i.e. access to byte 1,2 or 1,2,3 or 0,1,2 is not supported. The module will
respond with a bus error to such a transfer request. A data transfer to a valid local address is timed
out after 25.6
µ
sec with a BERR signal if the ProDAQ Bus does not respond.