3020-XX-UM
ProDAQ 3020 USB2.0 VXIbus Slot-0 Interface User Manual
Page 56 of 60
Copyright, © 2003 Bustec Production Ltd.
VXIbus Requester
Request Level
BR0 to BR3
Request Mode
“Fair” or “On Demand”
Release Mode
ROR, RWD
VXIbus Arbiter
Arbitration Mode
SGL, PRI, RRS
Arbitration Time-out
10 µs
VXIbus Interrupts
Interrupt Handler
IRQ1 to IRQ7
Interrupter
IRQ1 to IRQ7
Interrupter Release Mode
ROAK
6.7 Front Panel I/O
CLK10 In
Input Level
TTL
Input Protection
-5V to +10V
Connector Type
SMB
Note
When using an external clock to supply the CLK10 signal, you must use a VXIbus
standard compliant clock signal (10 MHz, equal or better than ±100 ppm, 50%±5%
duty cycle).
CLK10 Out
Output Level
TTL
Output Frequency*
10 MHz
Frequency Stability*
±100 ppm
Duty Cycle*
50%±5%
Connector Type
SMB
(* Specification valid for internal clock generator only)
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