BCM91125E
User Manual
04/27/05
B ro a d c o m C o r p o r a t i o n
Page 10
Firmware Configuration
Document
91125E-UM100-R
S e c t i o n 4 : F i r m w a r e C o n f i g u r a t i o n
This section contains information that is useful to software and firmware developers working with the board.
E
NDIANNESS
The firmware image in the flash is bi-endian, so it supports both big and little-endian operation. This can be
selected by Switch 4, Bit 2.
G
ENERIC
B
US
C
HIP
S
ELECTS
AND
M
EMORY
M
AP
Table 5 describes how the generic bus devices are connected to chip selects, and the default memory
addresses and sizings used by CFE. Programmers can alter the sizing of the blocks and the location in
memory of each chip select except CS0 by modifying CFE.
GPIO P
INS
Table 6 lists the wiring and firmware configuration for the BCM1125H GPIO pins.
Table 5: Generic Bus Chip Selects and Memory Map
Chip Select
Description
Physical Memory Address
Size
CS0
Boot ROM *
0x1FC0_0000
16 MB
CS1
Alternate Boot ROM *
0x1EC0_0000
16 MB
CS6
HP HDLO-2416 LED display
0x1D0A_0000
64 KB
* Intel® E28F128J3A boot flash memory or ROM emulator, depending on Switch 4 bit 0 setting (see Table 4).
Table 6: GPIO Map
GPIO Pin #
BCM1125H
Pin Direction
Description
0
Output
Debug LED.
1
Input
OUT from RTC.
6
Input
HyperTransport interrupt, HT_INT_L.
7
Input
PHY_INT_L (ORed PHY interrupt from both BCM5421 PHY chips).
8
Input
NMI_L from switch SW3.
9
Input
TEMP_ALERT_L from the temperature sensor.
Note:
All GPIO[15:0] pins are routed to the mezzanine connector as well. See Table 15 for details.
