2/24/2008 9T6WP
Preliminary Hardware Data Module
BCM7405
06/29/07
Functional Description
Bro a d c o m Co rp o r a ti o n
Document
7405-1HDM00-R
Peripherals Page 1-77
Baud Rate Generator
Each UART channel contains a baud rate generator that supplies the clock to the transmitter and receiver. The generator
consists of a 14-bit baud rate register and a 14-bit down counter. In operation, the counter decrements by one with each
generator clock and is automatically loaded with the contents of the baud rate register after the count reaches 0. The output
of the generator pulses when the counter reaches 0. The serial data bit rate and the baud rate generator input clock
frequency are related by the following formula:
This formula allows a bit rate of 1/16 to 1/262144 of the input frequency. For the BCM7405, the input frequency is 27 MHz.
Receiver
The receiver functions as a serial-to-parallel converter. The rxd pin is sampled at 16 times the data rate using a clock from
the Baud Rate Generator. A noise filtering circuit removes pulses with durations of less than 1 sample period. A sample taken
from the middle of a bit interval is used as the value for that bit. A false start bit that is not Low at the middle of the bit interval
is ignored. Received data bits are stored in a shift register. If the Parity Enable bit in the Control Register is asserted, the
receiver calculates the parity and compares it with the received parity bit. At the stop bit, the received data and 3 status bits
(Parity Error, Frame Error, Overrun) are written into the receive FIFO. The UART_RCVDATA Register is actually the receive
FIFO. Reading the UART_RCVDATA Register causes the FIFO to shift out the current data and status. The Receive Data
Available (RDA bit in the UART_RCVSTAT register) status is asserted whenever the FIFO has data.
G
ENERIC
I/O P
ORT
C
ONTROLLER
The BCM7405 contains 59 bits of general-purpose I/O that can be individually programmed to be either an input, output, or
open- drain output via control registers, and 8 bits of general-purpose I/O that can be individually programmed to either an
input or open-drain output. Each pin may be written or read via a control register. A read of a pin defined as an output or
open-drain output provided with external pull-up will verify that the state was programmed. If a GPIO pin is configured as an
input, it can be used to trigger an interrupt in the Peripheral Module interrupt register. Each GPIO pin has an individual
interrupt mask bit to turn off the interrupt function of the pin.
SPI M
ASTER
A SPI master allows the programming of external devices such as an access control chip. The MSPI within the BCM7405
provides easy peripheral expansion communication through the data_in, data_out, and serial_clock full-duplex synchronous
three-line bus. An internal RAM queue allows up to 16 serial transfers of 8-bits to 16-bits each, or the transmission of a single
data stream without CPU intervention. The MSPI also supports Wraparound mode, which allows continuous sampling of a
serial peripheral.
The MSPI communicates with external peripheral devices through a synchronous serial bus. The MSPI is compatible with
SPI systems found on other Motorola products; it can perform full-duplex three wire or half-duplex two-wire transfers.
The following features are supported on the MSPI within the BCM7405:
•
Full-duplex, three-wire synchronous transfers
•
Half-duplex, two-wire synchronous transfers
•
Programmable Clock polarity and phase
•
Programmable Queue—up to 16 preprogrammed transfers
bit_rate =
Input_Frequency
16 x (bau 1)
