2/24/2008 9T6WP
Preliminary Hardware Data Module
BCM7405
06/29/07
Functional Description
Bro a d c o m Co rp o r a ti o n
Document
7405-1HDM00-R
Data Transport Processor Page 1-27
local timestamp clock, plus a programmable offset, and adds the result to the existing PCR when the packet is output. This
maintains the accuracy of the PCR in the time shifted output packet stream.
The sync output tags the beginning of each transport packet.
Synchronizers allow the serial output of clock, data, and sync to be run from the following selected clocks:
•
IB0-5
•
81 MHz
•
54 MHz
•
40.5 MHz
•
27 MHz
•
20.25 MHz
The data transport supports two equivalent Remux modules i.e., Remux0 and Remux1, each programmed independently.
Remux1 module can output data either in serial of parallel output format. In parallel output format data is 8-bit wide. Whereas,
Remux0 can output data only in serial format.
PCR Recovery Block
The data transport design supports two equivalent PCR recovery circuits, each programmed independently.
Each data transport PCR module is capable of extracting the PCR information from a selected packet stream and generating
Timebase pulses (Timebase is a 27-MHz pulse train in 108-MHz clock domain) output that can be used by rate managers.
Each PCR module is also used to send the extracted PCRs directly to the audio and video decoders to ensure that both
decoders are using the same PCR.
Each VCXO generating 27-MHz system clock is locked to corresponding timebase pulse output from pcr_tb_loop.
The PCR module is programmed by the host CPU to search for a given PID. For MPEG streams, each time a PCR is found,
the 33-bit base and 9-bit extension are captured into a register, and the phase compare interrupt is asserted. At the same
time, the PCR load interrupt is pulsed if the host CPU has rewritten the PID register (with the valid bit set), or discontinuity
has occurred since the previous PCR was found.
When the PCR load interrupt occurs, the captured PCR is loaded into the system time clock (STC) counter. For MPEG mode,
the STC is configured with a 33-bit base and a 9-bit extension so that the base counter increments once every 300 27-MHz
ticks of the extension counter. The STC base counter is available for reading by the host CPU.
When the phase compare interrupt occurs, the current STC base and extension are latched. The latched STC values are
then compared to the latest PCR base and extension. Loop gain constants (FILT_A, FILT_B and FILT_C) are programmable
by the microprocessor to provide a degree of control to this filter. Loop filter is first order IIR filter. All LPF arithmetic is
saturating and phase saturation interrupt is generated if final output saturates.
Timebase loop allows the load integrator value to rapidly change the output frequency, but Broadcom does not normally
recommend this.
Two soft resets are also provided—one for the entire PCR module, and one that only resets this packet processor portion.
Note:
When outputting a playback channel, the output sync signal is generated by the playback sync extractor
module, so the ability to tag every packet depends on the integrity of the playback data stream and the ability
of the sync extractor module to lock to the playback data stream.
