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Broadcom

ACPL-C740-EvalKit-UG100

9

ACPL-C740 Evaluation Kit Board

 User Guide 

Isolated Sigma-Delta Modulator

PCB Modifications

1. Vdd1 is supplied from the 5V/5V isolated DC-DC converter using the push-pull transformer method. Vdd1 can also be 

supplied externally. To do that, ensure that R1 is disconnected.

2. The ACPL-C740 Vdd2 is supplied from the 3.3V regulator. To check the performance or troubleshoot the ACPL-C740 

component only at Vdd2 = 5V, short Pin 1 and Pin2 of the J5 connector on the C740-SDM-EVBDv2 board. The Vdd2 is 
then supplied directly from the USB power, 5VCC.
Note that R18 must be removed on the FPGA-EVBD board.

3. Green LED1–4 signals the detection of ACPL-C740. To modify the FPGA, use these LED indicators for other functions.

4. The H1 and H2 connector pins are physically connected to the FPGA. To modify the FPGA, use these connector pins 

for input (I/P) or input/output (I/O).

Troubleshooting

If the green DONE LED does not come on after switching on SW1, reset the FPGA by pressing SW2 once. If the problem 
arises, perform a full board reset by pressing SW3 once.

Each evaluation board is functionally checked and tested. before being sent to the customer. If a problem continues to arise, 
consult a Broadcom Application Engineer. If need be, Broadcom will send a new board.

Appendix

Figure 6:  PCB Description

ACPL-C740 

Isolated Sigma-

Delta Modulator

pSemi PE22100 
transformer driver

Shunt 

Resistor 

Mounting

SW1 board turn 

on switch

Xilinx Spartan 

XC3S250E 

FPGA

SW2 reset 

FPGA to 

default setting

USB 

Connector 

Interface

SW3 board 

power on 

sequence reset

Xilinx JTAG 

Interface

ACPL-C40 Low 

Voltage Side 

Connections

I/P pins 

physically 

connected to 

FPGA

I/O pins 

physically 

connected to 

FPGA

LED “5VIN” 

indicates 

presence of USB 

connection

USB UART / 

FIFO IC

EEPROM to 

store USB 

chipset 

settings

Nonvolatile flash 

memory to store 

FPGA bitfile

LED “DONE” 

indicates power 

on sequence 

complete

LED “HB” 

application 
software is 

running

LED “UPLOAD” 
indicates FPGA 

bitfile is being 

uploaded

Undefined LED 
2,3,4 Indicators

LED1-4 indicates 

that FPGA detects 

ACPL-C740

C740-SDM-Evbdv2

FPGA-Evbd

Wurth 750313638 
transformer coil

Ablic S-1200B50 

5V-5V voltage 

regulator

Isolated DC -DC Converter

Содержание ACPL-C740

Страница 1: ...tage as shown in Figure 1 A differential input signal of 0V ideally produces a data stream of ones 50 of the time and zeros 50 of the time A differential input of 200 mV corresponds to an 18 75 densit...

Страница 2: ...ng items ACPL C740 evaluation board Cable with USB mini USB terminations Softcopy folder containing drivers and application software programs The softcopy folder contains the following document or sof...

Страница 3: ...nce connected LED1 to LED4 light up in an undefined sequence to indicate that the board connections are properly done The C740 SDM EVBD and FPGA EVBD boards are shown respectively below 8 Go to the PC...

Страница 4: ...erage signal levels are shown in the time domain in terms of either mV or ADC count SNR SNDR 2nd harmonic and 3rd harmonic levels are displayed in the frequency domain 1 Click Start to begin capturing...

Страница 5: ...completion The FPGA LOAD Completed pop up appears as shown below 4 For quick help click Help from the top right corner of the application GUI then select the setup guide The help guide also describes...

Страница 6: ...ee provided sine wave files on a music player software program from the audio player devices described previously Adjust the volume until the signal level is near 200 mV or 20 000 ADC counts for best...

Страница 7: ...unt resistor until an input signal level of 200 mV is reached One such function generator is the ultra low distortion DS360 function generator from Standford Research Systems Table 3 shows the SNR SND...

Страница 8: ...of the PE22100 is selected as 100 pF which results in a switching frequency of around 200 kHz This frequency is outside the operating bandwidth of the ACPL C740 sigma delta modulator and the Sinc3 fi...

Страница 9: ...ng SW2 once If the problem arises perform a full board reset by pressing SW3 once Each evaluation board is functionally checked and tested before being sent to the customer If a problem continues to a...

Страница 10: ...BER FOOTER RF1 Vdd1 10 uF C15 VDD1 1 VIN 2 VIN 3 GND1 4 GND2 5 MDAT 6 MCLK 7 VDD2 8 U1 ACPL C740 0R R8 GND1 GND1 GND2 P1 RSHUNT P2 RSHUNT 0R R9 0R R10 RUBBER FOOTER RF2 RUBBER FOOTER RF3 RUBBER FOOTER...

Страница 11: ...om ACPL C740 EvalKit UG100 11 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator C740 SDM EVBD PCB Layout Figure 9 C740 SDM EVBD PCB Top Layer Figure 10 C740 SDM EVBD PCB Second...

Страница 12: ...Broadcom ACPL C740 EvalKit UG100 12 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator Figure 11 C740 SDM EVBD PCB Third Layer Figure 12 C740 SDM EVBD PCB Bottom Layer...

Страница 13: ...nloading FPGA Code For FPGA configuration via SPI only 1 2 FB2 1 2 FB1 470 R1 0 1 uF C2 GND2 27 R2 GND2 GND2 47 pF C11 GND2 27 R3 1 5K R6 0 47 uF C12 C34 GND2 0 1 uF C3 GND2 0 01 uF C1 GND2 1 2 DNM J1...

Страница 14: ...133 GND 61 GND 118 GND 127 U5 XC3S250E GND2 FTDI_D2 FTDI_D3 FTDI_D4 FTDI_D6 FTDI_D7 FTDI_RD USER_IO3 FTDI_WR USER_IO5 FTDI_D1 USER_IO26 USER_IO27 USER_IO28 USER_IO6 USER_IO7 USER_IO8 USER_IO9 USER_IN3...

Страница 15: ...Broadcom ACPL C740 EvalKit UG100 15 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator FPGA EVBD PCB Layout Figure 15 FPGA EVBD PCB Top Layer Figure 16 FPGA EVBD PCB Second Layer...

Страница 16: ...Broadcom ACPL C740 EvalKit UG100 16 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator Figure 17 FPGA EVBD PCB Third Layer Figure 18 FPGA EVBD PCB Bottom Layer...

Страница 17: ...ore information please visit www broadcom com Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability function or design Information fu...

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