1-4
1-28.
A HIGH is required at the input of coupler U11 when the external interlock is closed.
U11 will output a HIGH to OR gate U69B in the transmitter enable circuit. The HIGH
will configure U69B to output a HIGH to AND gate U71B. U71B will output a HIGH
cabinet command to allow the transmitter to be energized. U71B also outputs a HIGH to
NAND gate U71D. With a HIGH failĆsafe command, U71D will output a HIGH to
illuminate the interlock indicator. When the external interlock is opened, a LOW is
applied to U11. The output of U11 will go LOW. OR gate U69B will respond by
outputting a LOW to AND gate U71B. U71B will output a LOW cabinet command. A
LOW cabinet command configures a power control circuit to operate the transmitter to
off. U71D will output a LOW to: 1) extinguish the interlock indicator and 2) generate a
LOW operate command. A LOW operate command mutes: 1) the exciter PWM signal and
2) the power supply circuit board(s).
1-29.
Remote Control Fail-safe.
The remote control failĆsafe input is designed to accept a +5 to
+15 volt output from the remote control unit failĆsafe connection. The signal is optically
coupled to the controller circuitry by integrated circuit U56. Diode D23 protects the
circuit from a reverse polarity potential applied to the input.
1-30.
A HIGH is required at the input of U56 to indicate when the remote control unit is
operational. The output of coupler U56 will go HIGH. The HIGH will configure OR gate
U45C to output a HIGH failĆsafe signal. The failĆsafe signal is applied to AND gate
U71D. With a HIGH cabinet signal, U71D will output a HIGH to illuminate the interlock
indicator. The HIGH will also bias driver transistor Q48 on to illuminate remote failĆsafe
indicator DS2. When the remote control failĆsafe signal is removed, a LOW is applied to
U56. The output of U56 will go LOW. The LOW generates a LOW transmitter operate
command to mute: 1) the exciter PWM signal, 2) the power supply circuit board(s), and 3)
extinguish remote failĆsafe indicator DS2. The LOW from U56 will generate a LOW
failĆsafe command. The LOW is applied to U71D. U71D will output a LOW to extinguish
the interlock indicator.
1-31.
EXTERNAL MUTE.
The controller circuit board monitors the transmitter mute signal.
The external mute input is designed to accept a +5 to +15 volt output from an antenna
switch controller RF mute circuit. The signal is optically coupled to the controller
circuitry by U10. Diode D16 protects the circuit from a reverse polarity potential applied
to the input.
1-32.
A HIGH is required at the input of coupler U10 when the external mute circuit is
required to mute the transmitter RF power output. U10 will output a HIGH to OR gate
U13C and NOR gate U24A. U13C will output a HIGH to inverter U25A. U25A will
output a LOW to U22B. The LOW will configure U22B to output a LOW operate
command to mute: 1) the exciter PWM signal and 2) the power supply circuit board(s).
U24A will output a LOW to disable the antenna conflict indicator operations.
1-33.
ANTENNA INTERLOCK.
The controller circuit board is equipped with an antenna
interlock circuit. The circuit accepts: 1) control signals from power levels 2 through 5,
and 2) status inputs from three antenna systems. The antenna interlock circuit consists
of: 1) programming switches S1 through S3, 2) OR gates U12A/B and U21A/B, and
3) NAND gates U20A through U20D. The circuit analyzes the information and
determines if a correct antenna system and power level is selected for operation.
