23
JP7
:
Watchdog Timer Active Type Setting
Options
Settings
Active NMI
Short 1-2
System Reset (default)
Short 2-3
Disabled Watchdog Timer
Open
JP9 (5-10): WDT Timeout Period Select
Period
PINS 5-6 PINS 7-8 PINS 9-10
1 sec (default)
Short
Short
Short
2 sec
Open Short Short
10 sec
Short Open Short
20 sec
Open Open Short
110 sec
Short Short Open
220 sec
Open Short Open
The Watchdog Timer is disabled after the system Power-On. It can be
enabled via an Enable cycle and reading the control port (443H), or via
a Refresh cycle and reading the control port (443H), or via a Disable
cycle and reading the disable control port (045H).
After an Enable cycle of WDT, user must immediately execute a
Refresh cycle to WDT before its period setting comes to an end every
1, 2, 10, 20, 110 or 220 seconds. If the Refresh cycle does not activate
before WDT period cycle, the onboard WDT architecture will issue a
Reset or NMI cycle to the system. There are three I/O ports that control
the Watchdog Timer.
443H
I/O Read
The Enable cycle
443H
I/O Read
The Refresh cycle
045H
I/O Read
The Disable cycle
The following sample program shows how to Enable, Disable and
Refresh the Watchdog Timer
:
WDT_EN_RF EQU 0433H
WDT_DIS EQU
0045H
WT_Enable
PUSH
AX
; keep AX DX
PUSH
DX
MOV
DX,WDT_EN_RF
; enable the WDT
IN
AL,DX
POP
DX
; get back AX, DX
POP
AX
RET
WT_Refresh
PUSH
AX
; keep AX, DX
PUSH
DX
MOV
DX,WDT_ET_RF
; refresh the WDT
Содержание HS-6237
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