15
2.9 System Memory DRAM
All CPU Card provides a wide range on-board DRAM memory by two
pieces SIMM sockets (Bank0 & Bank1) to accept 1 MB, 2MB, 4MB,
8MB, 16MB, 32MB or 64MB. The SIMMs (Single In-Line Memory
Modules) RAM request the access time should be 70 n-second or
faster. The total capacity of the on board memory are between 2MB to
128MB.
See the figure on section 2.3 for get the identifying the banks. Please
take notes that the memory capacity of both SIMMs should be the same.
The Card requires
at least 2pcs of the RAM modules on
SIMM
socket.
2.10 Watch-Dog Timer
There are three access cycles of Watch-Dog Timer as Enable, Refresh
and Disable. The Enable cycle should proceed by READ PORT 443H.
The Disable cycle should proceed by READ PORT 043H. A continue
Enable cycle after a first Enable cycle means Refresh.
Once if the Enable cycle activity, a Refresh cycle is request before the
time-out period for restart counting the WDT Timer's period. Otherwise,
it will assume that the program operation is abnormal when the time
counting over the period preset of WDT Timer. A System Reset signal to
start again or a NMI cycle to the CPU comes if over.
The JP18 is using for select the active function of watch-dog timer in
disable the watch-dog timer, or presetting the watch-dog timer activity at
the reset trigger, or presetting the watch-dog timer activity at the NMI
trigger.
JP18 : Watch-Dog Active Type Setting
JP18 DESCRIPTION
*1-2
System Reset
2-3
Active NMI
OFF
disable Watch-dog timer
